drm/amd/display: Fix ODM combine data format
[Why] OPTC data format was left at its default value (444) when enabling ODM combine. This caused issues with FPGA capture. [How] Write the OPTC_DATA_FORMAT field when enabling ODM combine. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
2a874fa025
commit
fbc9ca671f
@ -463,6 +463,7 @@ struct dcn_optc_registers {
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type OPTC_SEG0_SRC_SEL;\
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type OPTC_SEG0_SRC_SEL;\
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type OPTC_SEG1_SRC_SEL;\
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type OPTC_SEG1_SRC_SEL;\
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type OPTC_MEM_SEL;\
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type OPTC_MEM_SEL;\
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type OPTC_DATA_FORMAT;\
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type OPTC_DSC_MODE;\
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type OPTC_DSC_MODE;\
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type OPTC_DSC_BYTES_PER_PIXEL;\
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type OPTC_DSC_BYTES_PER_PIXEL;\
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type OPTC_DSC_SLICE_WIDTH;\
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type OPTC_DSC_SLICE_WIDTH;\
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@ -703,7 +703,8 @@ enum dc_status dcn20_enable_stream_timing(
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pipe_ctx->stream_res.tg->funcs->set_odm_combine(
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pipe_ctx->stream_res.tg->funcs->set_odm_combine(
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pipe_ctx->stream_res.tg,
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pipe_ctx->stream_res.tg,
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odm_pipe->stream_res.opp->inst,
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odm_pipe->stream_res.opp->inst,
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pipe_ctx->stream->timing.h_addressable/2);
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pipe_ctx->stream->timing.h_addressable/2,
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pipe_ctx->stream->timing.pixel_encoding);
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/* HW program guide assume display already disable
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/* HW program guide assume display already disable
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* by unplug sequence. OTG assume stop.
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* by unplug sequence. OTG assume stop.
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*/
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*/
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@ -1007,7 +1008,8 @@ static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pip
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pipe_ctx->stream_res.tg->funcs->set_odm_combine(
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pipe_ctx->stream_res.tg->funcs->set_odm_combine(
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pipe_ctx->stream_res.tg,
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pipe_ctx->stream_res.tg,
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combine_pipe->stream_res.opp->inst,
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combine_pipe->stream_res.opp->inst,
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pipe_ctx->plane_res.scl_data.h_active);
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pipe_ctx->plane_res.scl_data.h_active,
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pipe_ctx->stream->timing.pixel_encoding);
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else
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else
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pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
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pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
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pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
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pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
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@ -238,11 +238,13 @@ void optc2_set_odm_bypass(struct timing_generator *optc,
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OPTC_MEM_SEL, 0);
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OPTC_MEM_SEL, 0);
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}
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}
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void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, int mpcc_hactive)
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void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
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int mpcc_hactive, enum dc_pixel_encoding pixel_encoding)
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{
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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/* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192 */
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/* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192 */
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int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf;
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int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf;
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uint32_t data_fmt = 0;
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/* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
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/* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
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* REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
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* REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
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@ -255,6 +257,13 @@ void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, in
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REG_SET(OPTC_MEMORY_CONFIG, 0,
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REG_SET(OPTC_MEMORY_CONFIG, 0,
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OPTC_MEM_SEL, memory_mask << (optc->inst * 4));
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OPTC_MEM_SEL, memory_mask << (optc->inst * 4));
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if (pixel_encoding == PIXEL_ENCODING_YCBCR422)
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data_fmt = 1;
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else if (pixel_encoding == PIXEL_ENCODING_YCBCR420)
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data_fmt = 2;
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REG_SET(OPTC_DATA_FORMAT_CONTROL, 0, OPTC_DATA_FORMAT, data_fmt);
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REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
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REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
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OPTC_NUM_OF_INPUT_SEGMENT, 1,
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OPTC_NUM_OF_INPUT_SEGMENT, 1,
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OPTC_SEG0_SRC_SEL, optc->inst,
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OPTC_SEG0_SRC_SEL, optc->inst,
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@ -66,6 +66,7 @@
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SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
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SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
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SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
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SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
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SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
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SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
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SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
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SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
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SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
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SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
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SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
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SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
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SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
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@ -95,7 +96,8 @@ void optc2_set_dsc_config(struct timing_generator *optc,
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void optc2_set_odm_bypass(struct timing_generator *optc,
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void optc2_set_odm_bypass(struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing);
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const struct dc_crtc_timing *dc_crtc_timing);
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void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, int mpcc_hactive);
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void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
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int mpcc_hactive, enum dc_pixel_encoding pixel_encoding);
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void optc2_get_optc_source(struct timing_generator *optc,
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void optc2_get_optc_source(struct timing_generator *optc,
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uint32_t *num_of_src_opp,
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uint32_t *num_of_src_opp,
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@ -268,7 +268,8 @@ struct timing_generator_funcs {
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uint32_t dsc_slice_width);
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uint32_t dsc_slice_width);
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#endif
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#endif
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void (*set_odm_bypass)(struct timing_generator *tg, const struct dc_crtc_timing *dc_crtc_timing);
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void (*set_odm_bypass)(struct timing_generator *tg, const struct dc_crtc_timing *dc_crtc_timing);
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void (*set_odm_combine)(struct timing_generator *tg, int combine_opp_id, int mpcc_hactive);
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void (*set_odm_combine)(struct timing_generator *tg, int combine_opp_id,
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int mpcc_hactive, enum dc_pixel_encoding pixel_encoding);
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void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
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void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
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void (*set_gsl_source_select)(struct timing_generator *optc,
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void (*set_gsl_source_select)(struct timing_generator *optc,
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int group_idx,
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int group_idx,
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