drm/amd/pm: update smu11 driver interface header for beige_goby
Use new struct name to identify beige_goby pptable due to extra added fields. v2: squash in updates (Alex) Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Evan Quan <Evan.Quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Chengming Gui
Alex Deucher
parent
5ed7715dbb
commit
fbe8115c6a
@ -129,8 +129,8 @@
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#define FEATURE_SMNCLK_DPM_BIT 47
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#define FEATURE_PERLINK_GMIDOWN_BIT 48
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#define FEATURE_GFX_EDC_BIT 49
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#define FEATURE_SPARE_50_BIT 50
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#define FEATURE_SPARE_51_BIT 51
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#define FEATURE_GFX_PER_PART_VMIN_BIT 50
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#define FEATURE_SMART_SHIFT_BIT 51
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#define FEATURE_SPARE_52_BIT 52
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#define FEATURE_SPARE_53_BIT 53
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#define FEATURE_SPARE_54_BIT 54
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@ -940,6 +940,367 @@ typedef struct {
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} PPTable_t;
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typedef struct {
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// MAJOR SECTION: SKU PARAMETERS
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uint32_t Version;
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// SECTION: Feature Enablement
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uint32_t FeaturesToRun[NUM_FEATURES / 32];
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// SECTION: Infrastructure Limits
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uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // Watts
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uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms
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uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // Watts
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uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms
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uint16_t TdcLimit[TDC_THROTTLER_COUNT]; // Amps
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uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms
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uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius
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uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime)
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// SECTION: Power Configuration
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uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e
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uint8_t TotalPowerPadding[3];
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// SECTION: APCC Settings
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uint32_t ApccPlusResidencyLimit;
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//SECTION: SMNCLK DPM
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uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS]; // in MHz
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uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2)
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uint32_t PaddingAPCC;
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uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2)
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uint16_t PaddingPerPartDroop;
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// SECTION: Throttler settings
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uint32_t ThrottlerControlMask; // See Throtter masks defines
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// SECTION: FW DSTATE Settings
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uint32_t FwDStateMask; // See FW DState masks defines
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// SECTION: ULV Settings
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uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
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uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
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uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
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uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
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uint16_t SocLIVmin;
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uint16_t SocLIVminoffset;
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uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events
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uint8_t paddingRlcUlvParams[3];
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// SECTION: Voltage Control Parameters
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uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
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uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
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uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
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uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
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uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits
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uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits
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// SECTION: Temperature Dependent Vmin
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uint16_t VDDGFX_TVmin; //Celcius
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uint16_t VDDSOC_TVmin; //Celcius
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uint16_t VDDGFX_Vmin_HiTemp; // mV Q2
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uint16_t VDDGFX_Vmin_LoTemp; // mV Q2
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uint16_t VDDSOC_Vmin_HiTemp; // mV Q2
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uint16_t VDDSOC_Vmin_LoTemp; // mV Q2
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uint16_t VDDGFX_TVminHystersis; // Celcius
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uint16_t VDDSOC_TVminHystersis; // Celcius
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//SECTION: DPM Config 1
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DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
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uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz
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uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz
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uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz
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uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz
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uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
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uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz
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uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz
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uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz
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uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz
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uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz
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uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
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uint32_t Paddingclks;
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DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format
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uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz
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uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8
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// Used for MALL performance boost
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uint16_t FclkBoostFreq; // In Mhz
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uint16_t FclkParamPadding;
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// SECTION: DPM Config 2
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uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz
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uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2)
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uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
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uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
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// GFXCLK DPM
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uint16_t GfxclkFgfxoffEntry; // in Mhz
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uint16_t GfxclkFinit; // in Mhz
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uint16_t GfxclkFidle; // in MHz
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uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL
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uint8_t GfxclkPadding;
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// GFX GPO
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uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM
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uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled
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uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled
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uint8_t GfxGpoPadding[1];
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uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation
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uint32_t GfxGpoPadding32[4];
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uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz
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uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz
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uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz
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uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase
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uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
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uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
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uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
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uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
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uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin.
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uint32_t DcsParamPadding[5];
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uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; // Q8.8
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// UCLK section
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uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only
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uint8_t PaddingMem[3];
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uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.
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// Used for 2-Step UCLK change workaround
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UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz
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UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz
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uint16_t UclkDpmMidstepFreq; // In Mhz
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uint16_t UclkMidstepPadding;
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// Link DPM Settings
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uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
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uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
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uint16_t LclkFreq[NUM_LINK_LEVELS];
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// SECTION: Fan Control
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uint16_t FanStopTemp; //Celcius
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uint16_t FanStartTemp; //Celcius
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uint16_t FanGain[TEMP_COUNT];
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uint16_t FanPwmMin;
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uint16_t FanAcousticLimitRpm;
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uint16_t FanThrottlingRpm;
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uint16_t FanMaximumRpm;
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uint16_t MGpuFanBoostLimitRpm;
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uint16_t FanTargetTemperature;
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uint16_t FanTargetGfxclk;
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uint16_t FanPadding16;
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uint8_t FanTempInputSelect;
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uint8_t FanPadding;
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uint8_t FanZeroRpmEnable;
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uint8_t FanTachEdgePerRev;
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// The following are AFC override parameters. Leave at 0 to use FW defaults.
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int16_t FuzzyFan_ErrorSetDelta;
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int16_t FuzzyFan_ErrorRateSetDelta;
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int16_t FuzzyFan_PwmSetDelta;
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uint16_t FuzzyFan_Reserved;
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// SECTION: AVFS
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// Overrides
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uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
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uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable)
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uint8_t Padding8_Avfs;
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QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve
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DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb
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DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb
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DroopInt_t dBtcGbSoc; // GHz->V BtcGb
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LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V
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PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format
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QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V
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uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2
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uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];
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uint8_t Padding8_GfxBtc[2];
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uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2
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uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2
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uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2
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// SECTION: XGMI
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uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3.
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uint8_t XgmiDpmSpare[2];
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// SECTION: Advanced Options
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uint32_t DebugOverrides;
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QuadraticInt_t ReservedEquation0;
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QuadraticInt_t ReservedEquation1;
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QuadraticInt_t ReservedEquation2;
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QuadraticInt_t ReservedEquation3;
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// SECTION: Sku Reserved
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uint8_t CustomerVariant;
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//VC BTC parameters are only applicable to VDD_GFX domain
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uint8_t VcBtcEnabled;
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uint16_t VcBtcVminT0; // T0_VMIN
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uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET
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uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB
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uint32_t VcBtcPsmA; // A_PSM
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uint32_t VcBtcPsmB; // B_PSM
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uint32_t VcBtcVminA; // A_VMIN
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uint32_t VcBtcVminB; // B_VMIN
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//GPIO Board feature
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uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs
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uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages
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uint32_t SkuReserved[16];
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// MAJOR SECTION: BOARD PARAMETERS
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//SECTION: Gaming Clocks
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uint32_t GamingClk[6];
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// SECTION: I2C Control
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I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
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uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1
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uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1
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uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off
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uint8_t I2cSpare[1];
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// SECTION: SVI2 Board Parameters
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uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
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uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
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uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
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uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
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uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
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uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
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uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
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uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
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// SECTION: Telemetry Settings
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uint16_t GfxMaxCurrent; // in Amps
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int8_t GfxOffset; // in Amps
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uint8_t Padding_TelemetryGfx;
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uint16_t SocMaxCurrent; // in Amps
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int8_t SocOffset; // in Amps
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uint8_t Padding_TelemetrySoc;
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uint16_t Mem0MaxCurrent; // in Amps
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int8_t Mem0Offset; // in Amps
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uint8_t Padding_TelemetryMem0;
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uint16_t Mem1MaxCurrent; // in Amps
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int8_t Mem1Offset; // in Amps
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uint8_t Padding_TelemetryMem1;
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uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
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// SECTION: GPIO Settings
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uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
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uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
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uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
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uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
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uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
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uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
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uint8_t GthrGpio; // GPIO pin configured for GTHR Event
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uint8_t GthrPolarity; // replace GPIO polarity for GTHR
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// LED Display Settings
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uint8_t LedPin0; // GPIO number for LedPin[0]
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uint8_t LedPin1; // GPIO number for LedPin[1]
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uint8_t LedPin2; // GPIO number for LedPin[2]
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uint8_t LedEnableMask;
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uint8_t LedPcie; // GPIO number for PCIE results
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uint8_t LedError; // GPIO number for Error Cases
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uint8_t LedSpare1[2];
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// SECTION: Clock Spread Spectrum
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// GFXCLK PLL Spread Spectrum
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uint8_t PllGfxclkSpreadEnabled; // on or off
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uint8_t PllGfxclkSpreadPercent; // Q4.4
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uint16_t PllGfxclkSpreadFreq; // kHz
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// GFXCLK DFLL Spread Spectrum
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uint8_t DfllGfxclkSpreadEnabled; // on or off
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uint8_t DfllGfxclkSpreadPercent; // Q4.4
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uint16_t DfllGfxclkSpreadFreq; // kHz
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// UCLK Spread Spectrum
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uint16_t UclkSpreadPadding;
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uint16_t UclkSpreadFreq; // kHz
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// FCLK Spread Spectrum
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uint8_t FclkSpreadEnabled; // on or off
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uint8_t FclkSpreadPercent; // Q4.4
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uint16_t FclkSpreadFreq; // kHz
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// Section: Memory Config
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uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
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uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
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uint8_t PaddingMem1[3];
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// Section: Total Board Power
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uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
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uint16_t BoardPowerPadding;
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// SECTION: XGMI Training
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uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS];
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uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS];
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uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS];
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uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS];
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// SECTION: UMC feature flags
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uint8_t HsrEnabled;
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uint8_t VddqOffEnabled;
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uint8_t PaddingUmcFlags[2];
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// UCLK Spread Spectrum
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uint8_t UclkSpreadPercent[16];
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// SECTION: Board Reserved
|
||||
uint32_t BoardReserved[11];
|
||||
|
||||
// SECTION: Structure Padding
|
||||
|
||||
// Padding for MMHUB - do not modify this
|
||||
uint32_t MmHubPadding[8]; // SMU internal use
|
||||
|
||||
|
||||
} PPTable_beige_goby_t;
|
||||
|
||||
typedef struct {
|
||||
// Time constant parameters for clock averages in ms
|
||||
uint16_t GfxclkAverageLpfTau;
|
||||
@ -1265,4 +1626,5 @@ typedef struct {
|
||||
// These defines are used with the SMC_MSG_SetUclkFastSwitch message.
|
||||
#define UCLK_SWITCH_SLOW 0
|
||||
#define UCLK_SWITCH_FAST 1
|
||||
#define UCLK_SWITCH_DUMMY 2
|
||||
#endif
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE
|
||||
#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x03
|
||||
#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF
|
||||
#define SMU11_DRIVER_IF_VERSION_Beige_Goby 0x7
|
||||
#define SMU11_DRIVER_IF_VERSION_Beige_Goby 0x9
|
||||
|
||||
/* MP Apertures */
|
||||
#define MP0_Public 0x03800000
|
||||
|
||||
Loading…
Reference in New Issue
Block a user