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drm: rcar-du: Stop accessing non-existent registers on gen4

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The following registers do not exist on gen4, so we should not write
them: DEF6Rm, DEF7Rm, DEF8Rm, ESCRn, OTARn.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
Tomi Valkeinen 2023-01-23 12:47:42 +02:00 committed by Laurent Pinchart
parent 5fbc2f3b91
commit fd228eb0b4
2 changed files with 19 additions and 13 deletions
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8
drivers/gpu/drm/rcar-du/rcar_du_crtc.c
View File

@ -298,10 +298,12 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
escr = params.escr;
}
dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
if (rcdu->info->gen < 4) {
dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
}
/* Signal polarities */
dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)

24
drivers/gpu/drm/rcar-du/rcar_du_group.c
View File

@ -148,19 +148,23 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
}
rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
rcar_du_group_setup_pins(rgrp);
if (rcdu->info->gen < 4)
rcar_du_group_setup_pins(rgrp);
/*
* TODO: Handle routing of the DU output to CMM dynamically, as we
* should bypass CMM completely when no color management feature is
* used.
*/
defr7 |= (rgrp->cmms_mask & BIT(1) ? DEFR7_CMME1 : 0) |
(rgrp->cmms_mask & BIT(0) ? DEFR7_CMME0 : 0);
rcar_du_group_write(rgrp, DEFR7, defr7);
if (rcdu->info->gen < 4) {
/*
* TODO: Handle routing of the DU output to CMM dynamically, as
* we should bypass CMM completely when no color management
* feature is used.
*/
defr7 |= (rgrp->cmms_mask & BIT(1) ? DEFR7_CMME1 : 0) |
(rgrp->cmms_mask & BIT(0) ? DEFR7_CMME0 : 0);
rcar_du_group_write(rgrp, DEFR7, defr7);
}
if (rcdu->info->gen >= 2) {
rcar_du_group_setup_defr8(rgrp);
if (rcdu->info->gen < 4)
rcar_du_group_setup_defr8(rgrp);
rcar_du_group_setup_didsr(rgrp);
}