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drm/i915/reg: use the correct register to access SAGV block time

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Wrong register address is used to read the SAG block time. Fix
the register address according to the bspec.

Bspec: 64608

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230323114426.41136-3-vinod.govindapillai@intel.com
This commit is contained in:
Vinod Govindapillai 2023-03-23 13:44:26 +02:00 committed by Stanislav Lisovskiy
parent ff168b37a9
commit fd6435ea32
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/i915_reg.h
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@ -7740,7 +7740,7 @@ enum skl_power_gate {
#define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0)
#define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16)
#define MTL_LATENCY_SAGV _MMIO(0x4578b)
#define MTL_LATENCY_SAGV _MMIO(0x4578c)
#define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0)
#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)