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media: cadence: csi2rx: configure DPHY before starting source stream

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When the source device is operating above 1.5 Gbps per lane, it needs to
send the Skew Calibration Sequence before sending any HS data. If the
DPHY is initialized after the source stream is started, then it might
miss the sequence and not be able to receive data properly. Move the
start of source subdev to the end of the sequence to make sure
everything is ready to receive data before the source starts streaming.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Fixes: 3295cf1241d3 ("media: cadence: Add support for external dphy")
Tested-by: Julien Massot <julien.massot@collabora.com>
Tested-by: Changhuang Liang <Changhuang.liang@starfivetech.com>
Reviewed-by: Julien Massot <julien.massot@collabora.com>
Reviewed-by: Changhuang Liang <Changhuang.liang@starfivetech.com>
Signed-off-by: Jai Luthra <j-luthra@ti.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
This commit is contained in:
Pratyush Yadav 2024-02-23 13:53:01 +05:30 committed by Hans Verkuil
parent 4bc6073615
commit fd64dda48f
1 changed files with 14 additions and 12 deletions
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26
drivers/media/platform/cadence/cdns-csi2rx.c
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@ -239,10 +239,6 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx)
writel(reg, csi2rx->base + CSI2RX_STATIC_CFG_REG); writel(reg, csi2rx->base + CSI2RX_STATIC_CFG_REG);
ret = v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, true);
if (ret)
goto err_disable_pclk;
/* Enable DPHY clk and data lanes. */ /* Enable DPHY clk and data lanes. */
if (csi2rx->dphy) { if (csi2rx->dphy) {
reg = CSI2RX_DPHY_CL_EN | CSI2RX_DPHY_CL_RST; reg = CSI2RX_DPHY_CL_EN | CSI2RX_DPHY_CL_RST;
@ -252,6 +248,13 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx)
} }
writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG);
ret = csi2rx_configure_ext_dphy(csi2rx);
if (ret) {
dev_err(csi2rx->dev,
"Failed to configure external DPHY: %d\n", ret);
goto err_disable_pclk;
}
} }
/* /*
@ -291,14 +294,9 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx)
reset_control_deassert(csi2rx->sys_rst); reset_control_deassert(csi2rx->sys_rst);
if (csi2rx->dphy) { ret = v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, true);
ret = csi2rx_configure_ext_dphy(csi2rx); if (ret)
if (ret) { goto err_disable_sysclk;
dev_err(csi2rx->dev,
"Failed to configure external DPHY: %d\n", ret);
goto err_disable_sysclk;
}
}
clk_disable_unprepare(csi2rx->p_clk); clk_disable_unprepare(csi2rx->p_clk);
@ -312,6 +310,10 @@ err_disable_pixclk:
clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); clk_disable_unprepare(csi2rx->pixel_clk[i - 1]);
} }
if (csi2rx->dphy) {
writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG);
phy_power_off(csi2rx->dphy);
}
err_disable_pclk: err_disable_pclk:
clk_disable_unprepare(csi2rx->p_clk); clk_disable_unprepare(csi2rx->p_clk);