tg3: Eliminate tg3_write_sig_post_reset() prototype
This patch moves the implementation of tg3_write_sig_post_reset() earlier to eliminate its prototype. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
committed by
David S. Miller
David S. Miller
parent
8d5a89b3da
commit
fd6d3f0ec7
@ -94,6 +94,10 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
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__stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
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__stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
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#define DRV_MODULE_RELDATE "August 18, 2011"
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#define DRV_MODULE_RELDATE "August 18, 2011"
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#define RESET_KIND_SHUTDOWN 0
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#define RESET_KIND_INIT 1
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#define RESET_KIND_SUSPEND 2
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#define TG3_DEF_RX_MODE 0
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#define TG3_DEF_RX_MODE 0
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#define TG3_DEF_TX_MODE 0
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#define TG3_DEF_TX_MODE 0
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#define TG3_DEF_MSG_ENABLE \
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#define TG3_DEF_MSG_ENABLE \
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@ -724,6 +728,103 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum)
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tg3_ape_write32(tp, gnt + 4 * locknum, bit);
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tg3_ape_write32(tp, gnt + 4 * locknum, bit);
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}
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}
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static void tg3_ape_send_event(struct tg3 *tp, u32 event)
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{
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int i;
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u32 apedata;
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/* NCSI does not support APE events */
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if (tg3_flag(tp, APE_HAS_NCSI))
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return;
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apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
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if (apedata != APE_SEG_SIG_MAGIC)
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return;
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apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
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if (!(apedata & APE_FW_STATUS_READY))
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return;
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/* Wait for up to 1 millisecond for APE to service previous event. */
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for (i = 0; i < 10; i++) {
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if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
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return;
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apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
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if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
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tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
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event | APE_EVENT_STATUS_EVENT_PENDING);
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tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
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if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
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break;
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udelay(100);
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}
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if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
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tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
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}
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static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
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{
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u32 event;
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u32 apedata;
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if (!tg3_flag(tp, ENABLE_APE))
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return;
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switch (kind) {
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case RESET_KIND_INIT:
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tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
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APE_HOST_SEG_SIG_MAGIC);
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tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
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APE_HOST_SEG_LEN_MAGIC);
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apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
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tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
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tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
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APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
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tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
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APE_HOST_BEHAV_NO_PHYLOCK);
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tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
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TG3_APE_HOST_DRVR_STATE_START);
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event = APE_EVENT_STATUS_STATE_START;
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break;
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case RESET_KIND_SHUTDOWN:
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/* With the interface we are currently using,
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* APE does not track driver state. Wiping
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* out the HOST SEGMENT SIGNATURE forces
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* the APE to assume OS absent status.
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*/
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tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
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if (device_may_wakeup(&tp->pdev->dev) &&
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tg3_flag(tp, WOL_ENABLE)) {
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tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
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TG3_APE_HOST_WOL_SPEED_AUTO);
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apedata = TG3_APE_HOST_DRVR_STATE_WOL;
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} else
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apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
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tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
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event = APE_EVENT_STATUS_STATE_UNLOAD;
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break;
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case RESET_KIND_SUSPEND:
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event = APE_EVENT_STATUS_STATE_SUSPEND;
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break;
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default:
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return;
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}
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event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
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tg3_ape_send_event(tp, event);
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}
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static void tg3_disable_ints(struct tg3 *tp)
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static void tg3_disable_ints(struct tg3 *tp)
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{
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{
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int i;
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int i;
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@ -1412,6 +1513,133 @@ static void tg3_stop_fw(struct tg3 *tp)
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}
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}
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}
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}
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/* tp->lock is held. */
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static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
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{
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tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
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NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
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if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
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switch (kind) {
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case RESET_KIND_INIT:
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tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
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DRV_STATE_START);
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break;
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case RESET_KIND_SHUTDOWN:
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tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
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DRV_STATE_UNLOAD);
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break;
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case RESET_KIND_SUSPEND:
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tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
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DRV_STATE_SUSPEND);
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break;
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default:
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break;
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}
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}
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if (kind == RESET_KIND_INIT ||
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kind == RESET_KIND_SUSPEND)
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tg3_ape_driver_state_change(tp, kind);
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}
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/* tp->lock is held. */
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static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
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{
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if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
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switch (kind) {
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case RESET_KIND_INIT:
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tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
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DRV_STATE_START_DONE);
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break;
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case RESET_KIND_SHUTDOWN:
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tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
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DRV_STATE_UNLOAD_DONE);
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break;
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default:
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break;
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}
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}
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if (kind == RESET_KIND_SHUTDOWN)
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tg3_ape_driver_state_change(tp, kind);
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}
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/* tp->lock is held. */
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static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
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{
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if (tg3_flag(tp, ENABLE_ASF)) {
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switch (kind) {
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case RESET_KIND_INIT:
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tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
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DRV_STATE_START);
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break;
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case RESET_KIND_SHUTDOWN:
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tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
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DRV_STATE_UNLOAD);
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break;
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case RESET_KIND_SUSPEND:
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tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
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DRV_STATE_SUSPEND);
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break;
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default:
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break;
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}
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}
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}
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static int tg3_poll_fw(struct tg3 *tp)
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{
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int i;
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u32 val;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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/* Wait up to 20ms for init done. */
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for (i = 0; i < 200; i++) {
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if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
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return 0;
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udelay(100);
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}
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return -ENODEV;
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}
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/* Wait for firmware initialization to complete. */
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for (i = 0; i < 100000; i++) {
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tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
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if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
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break;
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udelay(10);
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}
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/* Chip might not be fitted with firmware. Some Sun onboard
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* parts are configured like that. So don't signal the timeout
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* of the above loop as an error, but do report the lack of
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* running firmware once.
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*/
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if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
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tg3_flag_set(tp, NO_FWARE_REPORTED);
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netdev_info(tp->dev, "No firmware running\n");
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}
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if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
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/* The 57765 A0 needs a little more
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* time to do some important work.
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*/
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mdelay(10);
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}
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return 0;
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}
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static void tg3_link_report(struct tg3 *tp)
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static void tg3_link_report(struct tg3 *tp)
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{
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{
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if (!netif_carrier_ok(tp->dev)) {
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if (!netif_carrier_ok(tp->dev)) {
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@ -2503,12 +2731,6 @@ static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
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}
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}
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static int tg3_setup_phy(struct tg3 *, int);
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static int tg3_setup_phy(struct tg3 *, int);
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#define RESET_KIND_SHUTDOWN 0
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#define RESET_KIND_INIT 1
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#define RESET_KIND_SUSPEND 2
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static void tg3_write_sig_post_reset(struct tg3 *, int);
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static int tg3_halt_cpu(struct tg3 *, u32);
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static int tg3_halt_cpu(struct tg3 *, u32);
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static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
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static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
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@ -7145,230 +7367,6 @@ static int tg3_abort_hw(struct tg3 *tp, int silent)
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return err;
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return err;
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}
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}
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static void tg3_ape_send_event(struct tg3 *tp, u32 event)
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{
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int i;
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u32 apedata;
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/* NCSI does not support APE events */
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if (tg3_flag(tp, APE_HAS_NCSI))
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return;
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apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
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if (apedata != APE_SEG_SIG_MAGIC)
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return;
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apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
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if (!(apedata & APE_FW_STATUS_READY))
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return;
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/* Wait for up to 1 millisecond for APE to service previous event. */
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for (i = 0; i < 10; i++) {
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if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
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return;
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apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
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if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
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tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
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event | APE_EVENT_STATUS_EVENT_PENDING);
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tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
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if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
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break;
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udelay(100);
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}
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if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
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tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
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}
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static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
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{
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u32 event;
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u32 apedata;
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if (!tg3_flag(tp, ENABLE_APE))
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return;
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switch (kind) {
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case RESET_KIND_INIT:
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tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
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APE_HOST_SEG_SIG_MAGIC);
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tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
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APE_HOST_SEG_LEN_MAGIC);
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apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
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tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
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tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
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APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
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tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
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APE_HOST_BEHAV_NO_PHYLOCK);
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tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
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TG3_APE_HOST_DRVR_STATE_START);
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event = APE_EVENT_STATUS_STATE_START;
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break;
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case RESET_KIND_SHUTDOWN:
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/* With the interface we are currently using,
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* APE does not track driver state. Wiping
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* out the HOST SEGMENT SIGNATURE forces
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* the APE to assume OS absent status.
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*/
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tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
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if (device_may_wakeup(&tp->pdev->dev) &&
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tg3_flag(tp, WOL_ENABLE)) {
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tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
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TG3_APE_HOST_WOL_SPEED_AUTO);
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apedata = TG3_APE_HOST_DRVR_STATE_WOL;
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} else
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apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
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tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
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|
||||||
event = APE_EVENT_STATUS_STATE_UNLOAD;
|
|
||||||
break;
|
|
||||||
case RESET_KIND_SUSPEND:
|
|
||||||
event = APE_EVENT_STATUS_STATE_SUSPEND;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
|
|
||||||
|
|
||||||
tg3_ape_send_event(tp, event);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* tp->lock is held. */
|
|
||||||
static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
|
|
||||||
{
|
|
||||||
tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
|
|
||||||
NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
|
|
||||||
|
|
||||||
if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
|
|
||||||
switch (kind) {
|
|
||||||
case RESET_KIND_INIT:
|
|
||||||
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
|
|
||||||
DRV_STATE_START);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case RESET_KIND_SHUTDOWN:
|
|
||||||
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
|
|
||||||
DRV_STATE_UNLOAD);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case RESET_KIND_SUSPEND:
|
|
||||||
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
|
|
||||||
DRV_STATE_SUSPEND);
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (kind == RESET_KIND_INIT ||
|
|
||||||
kind == RESET_KIND_SUSPEND)
|
|
||||||
tg3_ape_driver_state_change(tp, kind);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* tp->lock is held. */
|
|
||||||
static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
|
|
||||||
{
|
|
||||||
if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
|
|
||||||
switch (kind) {
|
|
||||||
case RESET_KIND_INIT:
|
|
||||||
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
|
|
||||||
DRV_STATE_START_DONE);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case RESET_KIND_SHUTDOWN:
|
|
||||||
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
|
|
||||||
DRV_STATE_UNLOAD_DONE);
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (kind == RESET_KIND_SHUTDOWN)
|
|
||||||
tg3_ape_driver_state_change(tp, kind);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* tp->lock is held. */
|
|
||||||
static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
|
|
||||||
{
|
|
||||||
if (tg3_flag(tp, ENABLE_ASF)) {
|
|
||||||
switch (kind) {
|
|
||||||
case RESET_KIND_INIT:
|
|
||||||
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
|
|
||||||
DRV_STATE_START);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case RESET_KIND_SHUTDOWN:
|
|
||||||
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
|
|
||||||
DRV_STATE_UNLOAD);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case RESET_KIND_SUSPEND:
|
|
||||||
tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
|
|
||||||
DRV_STATE_SUSPEND);
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static int tg3_poll_fw(struct tg3 *tp)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
u32 val;
|
|
||||||
|
|
||||||
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
|
|
||||||
/* Wait up to 20ms for init done. */
|
|
||||||
for (i = 0; i < 200; i++) {
|
|
||||||
if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
|
|
||||||
return 0;
|
|
||||||
udelay(100);
|
|
||||||
}
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Wait for firmware initialization to complete. */
|
|
||||||
for (i = 0; i < 100000; i++) {
|
|
||||||
tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
|
|
||||||
if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
|
|
||||||
break;
|
|
||||||
udelay(10);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Chip might not be fitted with firmware. Some Sun onboard
|
|
||||||
* parts are configured like that. So don't signal the timeout
|
|
||||||
* of the above loop as an error, but do report the lack of
|
|
||||||
* running firmware once.
|
|
||||||
*/
|
|
||||||
if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
|
|
||||||
tg3_flag_set(tp, NO_FWARE_REPORTED);
|
|
||||||
|
|
||||||
netdev_info(tp->dev, "No firmware running\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
|
|
||||||
/* The 57765 A0 needs a little more
|
|
||||||
* time to do some important work.
|
|
||||||
*/
|
|
||||||
mdelay(10);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Save PCI command register before chip reset */
|
/* Save PCI command register before chip reset */
|
||||||
static void tg3_save_pci_state(struct tg3 *tp)
|
static void tg3_save_pci_state(struct tg3 *tp)
|
||||||
{
|
{
|
||||||
|
|||||||
Reference in New Issue
Block a user