From fda48d15a4eade29a41d46d5a6f0bfa7556ccb72 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Wed, 26 Jul 2023 09:07:08 -0700 Subject: [PATCH] drm/xe: Sort xe_regs.h Sort it by register address to make it easy to update when needed. v2: Do not create exception for registers with same functionality. Always sort it. Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20230726160708.3967790-11-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/regs/xe_regs.h | 69 ++++++++++++++++--------------- 1 file changed, 36 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index b344796bb868..25275a36b280 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -7,9 +7,6 @@ #include "regs/xe_reg_defs.h" -#define GU_CNTL XE_REG(0x101010) -#define LMEM_INIT REG_BIT(7) - #define RENDER_RING_BASE 0x02000 #define BSD_RING_BASE 0x1c0000 #define BSD2_RING_BASE 0x1c4000 @@ -45,16 +42,13 @@ #define FF_THREAD_MODE XE_REG(0x20a0) #define FF_TESSELATION_DOP_GATE_DISABLE BIT(19) -#define PVC_RP_STATE_CAP XE_REG(0x281014) -#define MTL_RP_STATE_CAP XE_REG(0x138000) +#define TIMESTAMP_OVERRIDE XE_REG(0x44074) +#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK REG_GENMASK(15, 12) +#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK REG_GENMASK(9, 0) -#define MTL_MEDIAP_STATE_CAP XE_REG(0x138020) -#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) -#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) - -#define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c) -#define MTL_MPE_FREQUENCY XE_REG(0x13802c) -#define MTL_RPE_MASK REG_GENMASK(8, 0) +#define PCU_IRQ_OFFSET 0x444e0 +#define GU_MISC_IRQ_OFFSET 0x444f0 +#define GU_MISC_GSE REG_BIT(27) #define TRANSCODER_A_OFFSET 0x60000 #define TRANSCODER_B_OFFSET 0x61000 @@ -71,9 +65,35 @@ #define SOFTWARE_FLAGS_SPR33 XE_REG(0x4f084) -#define PCU_IRQ_OFFSET 0x444e0 -#define GU_MISC_IRQ_OFFSET 0x444f0 -#define GU_MISC_GSE REG_BIT(27) +#define GU_CNTL XE_REG(0x101010) +#define LMEM_INIT REG_BIT(7) + +#define GGC XE_REG(0x108040) +#define GMS_MASK REG_GENMASK(15, 8) +#define GGMS_MASK REG_GENMASK(7, 6) + +#define DSMBASE XE_REG(0x1080C0) +#define BDSM_MASK REG_GENMASK64(63, 20) + +#define GSMBASE XE_REG(0x108100) + +#define STOLEN_RESERVED XE_REG(0x1082c0) +#define WOPCM_SIZE_MASK REG_GENMASK64(8, 7) + +#define MTL_RP_STATE_CAP XE_REG(0x138000) + +#define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c) + +#define MTL_MEDIAP_STATE_CAP XE_REG(0x138020) +#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) +#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) + +#define MTL_MPE_FREQUENCY XE_REG(0x13802c) +#define MTL_RPE_MASK REG_GENMASK(8, 0) + +#define DG1_MSTR_TILE_INTR XE_REG(0x190008) +#define DG1_MSTR_IRQ REG_BIT(31) +#define DG1_MSTR_TILE(t) REG_BIT(t) #define GFX_MSTR_IRQ XE_REG(0x190010) #define MASTER_IRQ REG_BIT(31) @@ -81,23 +101,6 @@ #define DISPLAY_IRQ REG_BIT(16) #define GT_DW_IRQ(x) REG_BIT(x) -#define DG1_MSTR_TILE_INTR XE_REG(0x190008) -#define DG1_MSTR_IRQ REG_BIT(31) -#define DG1_MSTR_TILE(t) REG_BIT(t) - -#define TIMESTAMP_OVERRIDE XE_REG(0x44074) -#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK REG_GENMASK(15, 12) -#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK REG_GENMASK(9, 0) - -#define GGC XE_REG(0x108040) -#define GMS_MASK REG_GENMASK(15, 8) -#define GGMS_MASK REG_GENMASK(7, 6) - -#define GSMBASE XE_REG(0x108100) -#define DSMBASE XE_REG(0x1080C0) -#define BDSM_MASK REG_GENMASK64(63, 20) - -#define STOLEN_RESERVED XE_REG(0x1082c0) -#define WOPCM_SIZE_MASK REG_GENMASK64(8, 7) +#define PVC_RP_STATE_CAP XE_REG(0x281014) #endif