adm8211: fixed the possible pci cache line sizes inside switch-case

The PCI cache line size value was being compared against decimal values
prefixed with 0x.

Fixed the literals to use the correct hex values.

This has not been tested due to lack of hardware. However, the value in
`cline` is PCI cache line size, which is the CPU's cache line size.
It is less likely for cache line sizes to be 22 or 50, and more likely for
them to be 16 or 32. Also, as far as I understand, cache line size is used for
things like aligning DMA requests with CPU cache line, which improve
performance but wouldn't break anything if the value doesn't match. In
this case, we will fall through to the default case which leaves `reg`
unchanged.

Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

drivers/net/wireless/adm8211.c

@@ -1101,10 +1101,10 @@ static void adm8211_hw_init(struct ieee80211_hw *dev)
 		case  0x8:
 			reg |= (0x1 << 14);
 			break;
-		case 0x16:
+		case 0x10:
 			reg |= (0x2 << 14);
 			break;
-		case 0x32:
+		case 0x20:
 			reg |= (0x3 << 14);
 			break;
 		default: