- amd64_edac: Add support for three-rank interleaving mode which is
present on AMD zen2 servers
- The usual fixes and cleanups all over EDAC land
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Merge tag 'edac_updates_for_v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras
Pull EDAC updates from Borislav Petkov:
"A small pile of EDAC updates which the autumn wind blew my way. :)
- amd64_edac: Add support for three-rank interleaving mode which is
present on AMD zen2 servers
- The usual fixes and cleanups all over EDAC land"
* tag 'edac_updates_for_v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
EDAC/sb_edac: Fix top-of-high-memory value for Broadwell/Haswell
EDAC/ti: Remove redundant error messages
EDAC/amd64: Handle three rank interleaving mode
EDAC/mc_sysfs: Print MC-scope sysfs counters unsigned
EDAC/al_mc: Make use of the helper function devm_add_action_or_reset()
EDAC/mc: Replace strcpy(), sprintf() and snprintf() with strscpy() or scnprintf()
This commit is contained in:
Linus Torvalds
commit
fe354159ca
@ -238,11 +238,9 @@ static int al_mc_edac_probe(struct platform_device *pdev)
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if (!mci)
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return -ENOMEM;
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ret = devm_add_action(&pdev->dev, devm_al_mc_edac_free, mci);
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if (ret) {
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edac_mc_free(mci);
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ret = devm_add_action_or_reset(&pdev->dev, devm_al_mc_edac_free, mci);
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if (ret)
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return ret;
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}
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platform_set_drvdata(pdev, mci);
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al_mc = mci->pvt_info;
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@ -293,11 +291,9 @@ static int al_mc_edac_probe(struct platform_device *pdev)
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return ret;
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}
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ret = devm_add_action(&pdev->dev, devm_al_mc_edac_del, &pdev->dev);
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if (ret) {
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edac_mc_del_mc(&pdev->dev);
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ret = devm_add_action_or_reset(&pdev->dev, devm_al_mc_edac_del, &pdev->dev);
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if (ret)
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return ret;
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}
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if (al_mc->irq_ue > 0) {
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ret = devm_request_irq(&pdev->dev,
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@ -1065,12 +1065,14 @@ static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
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#define CS_ODD_PRIMARY BIT(1)
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#define CS_EVEN_SECONDARY BIT(2)
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#define CS_ODD_SECONDARY BIT(3)
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#define CS_3R_INTERLEAVE BIT(4)
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#define CS_EVEN (CS_EVEN_PRIMARY | CS_EVEN_SECONDARY)
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#define CS_ODD (CS_ODD_PRIMARY | CS_ODD_SECONDARY)
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static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt)
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{
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u8 base, count = 0;
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int cs_mode = 0;
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if (csrow_enabled(2 * dimm, ctrl, pvt))
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@ -1083,6 +1085,20 @@ static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt)
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if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt))
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cs_mode |= CS_ODD_SECONDARY;
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/*
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* 3 Rank inteleaving support.
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* There should be only three bases enabled and their two masks should
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* be equal.
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*/
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for_each_chip_select(base, ctrl, pvt)
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count += csrow_enabled(base, ctrl, pvt);
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if (count == 3 &&
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pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) {
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edac_dbg(1, "3R interleaving in use.\n");
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cs_mode |= CS_3R_INTERLEAVE;
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}
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return cs_mode;
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}
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@ -1891,10 +1907,14 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
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*
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* The MSB is the number of bits in the full mask because BIT[0] is
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* always 0.
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*
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* In the special 3 Rank interleaving case, a single bit is flipped
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* without swapping with the most significant bit. This can be handled
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* by keeping the MSB where it is and ignoring the single zero bit.
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*/
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msb = fls(addr_mask_orig) - 1;
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weight = hweight_long(addr_mask_orig);
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num_zero_bits = msb - weight;
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num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE);
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/* Take the number of zero bits off from the top of the mask. */
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addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1);
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@ -66,14 +66,12 @@ unsigned int edac_dimm_info_location(struct dimm_info *dimm, char *buf,
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char *p = buf;
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for (i = 0; i < mci->n_layers; i++) {
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n = snprintf(p, len, "%s %d ",
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n = scnprintf(p, len, "%s %d ",
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edac_layer_name[mci->layers[i].type],
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dimm->location[i]);
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p += n;
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len -= n;
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count += n;
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if (!len)
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break;
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}
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return count;
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@ -341,19 +339,16 @@ static int edac_mc_alloc_dimms(struct mem_ctl_info *mci)
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*/
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len = sizeof(dimm->label);
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p = dimm->label;
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n = snprintf(p, len, "mc#%u", mci->mc_idx);
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n = scnprintf(p, len, "mc#%u", mci->mc_idx);
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p += n;
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len -= n;
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for (layer = 0; layer < mci->n_layers; layer++) {
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n = snprintf(p, len, "%s#%u",
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edac_layer_name[mci->layers[layer].type],
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pos[layer]);
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n = scnprintf(p, len, "%s#%u",
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edac_layer_name[mci->layers[layer].type],
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pos[layer]);
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p += n;
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len -= n;
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dimm->location[layer] = pos[layer];
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if (len <= 0)
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break;
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}
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/* Link it to the csrows old API data */
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@ -1027,12 +1022,13 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
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const char *other_detail)
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{
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struct dimm_info *dimm;
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char *p;
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char *p, *end;
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int row = -1, chan = -1;
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int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer };
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int i, n_labels = 0;
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struct edac_raw_error_desc *e = &mci->error_desc;
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bool any_memory = true;
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const char *prefix;
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edac_dbg(3, "MC%d\n", mci->mc_idx);
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@ -1087,6 +1083,8 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
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*/
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p = e->label;
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*p = '\0';
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end = p + sizeof(e->label);
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prefix = "";
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mci_for_each_dimm(mci, dimm) {
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if (top_layer >= 0 && top_layer != dimm->location[0])
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@ -1114,12 +1112,8 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
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p = e->label;
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*p = '\0';
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} else {
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if (p != e->label) {
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strcpy(p, OTHER_LABEL);
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p += strlen(OTHER_LABEL);
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}
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strcpy(p, dimm->label);
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p += strlen(p);
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p += scnprintf(p, end - p, "%s%s", prefix, dimm->label);
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prefix = OTHER_LABEL;
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}
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/*
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@ -1141,25 +1135,25 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
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}
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if (any_memory)
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strcpy(e->label, "any memory");
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strscpy(e->label, "any memory", sizeof(e->label));
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else if (!*e->label)
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strcpy(e->label, "unknown memory");
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strscpy(e->label, "unknown memory", sizeof(e->label));
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edac_inc_csrow(e, row, chan);
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/* Fill the RAM location data */
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p = e->location;
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end = p + sizeof(e->location);
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prefix = "";
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for (i = 0; i < mci->n_layers; i++) {
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if (pos[i] < 0)
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continue;
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p += sprintf(p, "%s:%d ",
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edac_layer_name[mci->layers[i].type],
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pos[i]);
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p += scnprintf(p, end - p, "%s%s:%d", prefix,
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edac_layer_name[mci->layers[i].type], pos[i]);
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prefix = " ";
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}
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if (p > e->location)
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*(p - 1) = '\0';
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edac_raw_mc_handle_error(e);
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}
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@ -744,7 +744,7 @@ static ssize_t mci_ue_count_show(struct device *dev,
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{
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struct mem_ctl_info *mci = to_mci(dev);
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return sprintf(data, "%d\n", mci->ue_mc);
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return sprintf(data, "%u\n", mci->ue_mc);
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}
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static ssize_t mci_ce_count_show(struct device *dev,
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@ -753,7 +753,7 @@ static ssize_t mci_ce_count_show(struct device *dev,
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{
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struct mem_ctl_info *mci = to_mci(dev);
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return sprintf(data, "%d\n", mci->ce_mc);
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return sprintf(data, "%u\n", mci->ce_mc);
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}
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static ssize_t mci_ce_noinfo_show(struct device *dev,
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@ -762,7 +762,7 @@ static ssize_t mci_ce_noinfo_show(struct device *dev,
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{
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struct mem_ctl_info *mci = to_mci(dev);
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return sprintf(data, "%d\n", mci->ce_noinfo_count);
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return sprintf(data, "%u\n", mci->ce_noinfo_count);
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}
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static ssize_t mci_ue_noinfo_show(struct device *dev,
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@ -771,7 +771,7 @@ static ssize_t mci_ue_noinfo_show(struct device *dev,
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{
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struct mem_ctl_info *mci = to_mci(dev);
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return sprintf(data, "%d\n", mci->ue_noinfo_count);
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return sprintf(data, "%u\n", mci->ue_noinfo_count);
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}
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static ssize_t mci_seconds_show(struct device *dev,
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@ -1052,7 +1052,7 @@ static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
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pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®);
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rc = ((reg << 6) | rc) << 26;
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return rc | 0x1ffffff;
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return rc | 0x3ffffff;
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}
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static u64 knl_get_tolm(struct sbridge_pvt *pvt)
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@ -245,11 +245,8 @@ static int ti_edac_probe(struct platform_device *pdev)
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(dev, res);
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if (IS_ERR(reg)) {
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edac_printk(KERN_ERR, EDAC_MOD_NAME,
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"EMIF controller regs not defined\n");
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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}
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layers[0].type = EDAC_MC_LAYER_ALL_MEM;
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layers[0].size = 1;
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@ -281,8 +278,6 @@ static int ti_edac_probe(struct platform_device *pdev)
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error_irq = platform_get_irq(pdev, 0);
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if (error_irq < 0) {
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ret = error_irq;
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edac_printk(KERN_ERR, EDAC_MOD_NAME,
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"EMIF irq number not defined.\n");
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goto err;
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}
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Block a user