drm/xe/mtl: Reduce Wa_14018575942 scope to the CCS engine
The MTL version of Wa_14018575942 has been updated to suggest only applying the register change on the CCS engine. Note that DG2 and PVC have a functionally equivalent workaround with Wa_18018781329; for now that one is still applying to all engines, although we'll keep an eye on it in case it changes to be CCS-specific too. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/20230728175601.2343755-2-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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@ -238,21 +238,13 @@ static const struct xe_rtp_entry_sr gt_was[] = {
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},
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{ XE_RTP_NAME("14018575942"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
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XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
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SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
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XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
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},
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{ XE_RTP_NAME("22016670082"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
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XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
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},
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/* Xe_LPM+ */
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{ XE_RTP_NAME("14018575942"),
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XE_RTP_RULES(MEDIA_VERSION(1300)),
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XE_RTP_ACTIONS(SET(XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
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SET(XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
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},
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{}
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};
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