soc: imx: gpcv2: add support for optional resets
Normally the reset for the devices inside the power domain is triggered automatically from the PGC in the power-up sequencing, however on i.MX8MM this doesn't work for the GPU power domains. Add support for triggering the reset explicitly during the power up sequencing. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -15,6 +15,7 @@
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/sizes.h>
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#include <dt-bindings/power/imx7-power.h>
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#include <dt-bindings/power/imx8mq-power.h>
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@ -108,6 +109,7 @@ struct imx_pgc_domain {
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struct generic_pm_domain genpd;
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struct regmap *regmap;
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struct regulator *regulator;
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struct reset_control *reset;
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struct clk_bulk_data *clks;
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int num_clks;
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@ -163,6 +165,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
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goto out_regulator_disable;
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}
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reset_control_assert(domain->reset);
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if (domain->bits.pxx) {
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/* request the domain to power up */
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regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
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@ -185,6 +189,11 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
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GPC_PGC_CTRL_PCR);
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}
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/* delay for reset to propagate */
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udelay(5);
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reset_control_deassert(domain->reset);
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/* request the ADB400 to power up */
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if (domain->bits.hskreq) {
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regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
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@ -540,6 +549,11 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
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return dev_err_probe(domain->dev, domain->num_clks,
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"Failed to get domain's clocks\n");
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domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev);
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if (IS_ERR(domain->reset))
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return dev_err_probe(domain->dev, PTR_ERR(domain->reset),
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"Failed to get domain's resets\n");
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pm_runtime_enable(domain->dev);
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if (domain->bits.map)
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