RDMA/mlx5: Expose wqe posting helpers outside of wr.c
Split posting WQEs logic to helpers, generalize it and expose for future use in the UMR post send. Link: https://lore.kernel.org/r/a2b0f6cd96f0405a65d38e82c6ae7ef34dcb34bc.1649747695.git.leonro@nvidia.com Signed-off-by: Aharon Landau <aharonl@nvidia.com> Reviewed-by: Michael Guralnik <michaelgur@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Aharon Landau
Jason Gunthorpe
parent
ba6a9c6899
commit
fe765aeb77
@ -26,58 +26,7 @@ static const u32 mlx5_ib_opcode[] = {
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[MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
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};
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/* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
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* next nearby edge and get new address translation for current WQE position.
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* @sq - SQ buffer.
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* @seg: Current WQE position (16B aligned).
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* @wqe_sz: Total current WQE size [16B].
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* @cur_edge: Updated current edge.
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*/
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static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
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u32 wqe_sz, void **cur_edge)
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{
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u32 idx;
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if (likely(*seg != *cur_edge))
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return;
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idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
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*cur_edge = get_sq_edge(sq, idx);
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*seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
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}
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/* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
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* pointers. At the end @seg is aligned to 16B regardless the copied size.
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* @sq - SQ buffer.
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* @cur_edge: Updated current edge.
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* @seg: Current WQE position (16B aligned).
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* @wqe_sz: Total current WQE size [16B].
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* @src: Pointer to copy from.
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* @n: Number of bytes to copy.
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*/
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static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
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void **seg, u32 *wqe_sz, const void *src,
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size_t n)
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{
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while (likely(n)) {
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size_t leftlen = *cur_edge - *seg;
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size_t copysz = min_t(size_t, leftlen, n);
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size_t stride;
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memcpy(*seg, src, copysz);
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n -= copysz;
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src += copysz;
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stride = !n ? ALIGN(copysz, 16) : copysz;
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*seg += stride;
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*wqe_sz += stride >> 4;
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handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
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}
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}
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static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq,
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struct ib_cq *ib_cq)
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int mlx5r_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
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{
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struct mlx5_ib_cq *cq;
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unsigned int cur;
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@ -123,9 +72,9 @@ static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
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eseg->mss = cpu_to_be16(ud_wr->mss);
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eseg->inline_hdr.sz = cpu_to_be16(left);
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/* memcpy_send_wqe should get a 16B align address. Hence, we
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* first copy up to the current edge and then, if needed,
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* continue to memcpy_send_wqe.
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/* mlx5r_memcpy_send_wqe should get a 16B align address. Hence,
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* we first copy up to the current edge and then, if needed,
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* continue to mlx5r_memcpy_send_wqe.
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*/
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copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
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left);
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@ -139,8 +88,8 @@ static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
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handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
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left -= copysz;
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pdata += copysz;
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memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
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left);
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mlx5r_memcpy_send_wqe(&qp->sq, cur_edge, seg, size,
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pdata, left);
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}
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return;
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@ -766,8 +715,8 @@ static int set_reg_wr(struct mlx5_ib_qp *qp,
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handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
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if (umr_inline) {
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memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
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mr_list_size);
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mlx5r_memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
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mr_list_size);
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*size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
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} else {
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set_reg_data_seg(*seg, mr, pd);
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@ -809,23 +758,22 @@ static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
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}
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}
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static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
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struct mlx5_wqe_ctrl_seg **ctrl,
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const struct ib_send_wr *wr, unsigned int *idx,
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int *size, void **cur_edge, int nreq,
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bool send_signaled, bool solicited)
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int mlx5r_begin_wqe(struct mlx5_ib_qp *qp, void **seg,
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struct mlx5_wqe_ctrl_seg **ctrl, unsigned int *idx,
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int *size, void **cur_edge, int nreq, __be32 general_id,
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bool send_signaled, bool solicited)
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{
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if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
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if (unlikely(mlx5r_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
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return -ENOMEM;
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*idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
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*seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
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*ctrl = *seg;
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*(uint32_t *)(*seg + 8) = 0;
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(*ctrl)->imm = send_ieth(wr);
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(*ctrl)->general_id = general_id;
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(*ctrl)->fm_ce_se = qp->sq_signal_bits |
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(send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
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(solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
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(send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
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(solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
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*seg += sizeof(**ctrl);
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*size = sizeof(**ctrl) / 16;
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@ -839,16 +787,14 @@ static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
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const struct ib_send_wr *wr, unsigned int *idx, int *size,
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void **cur_edge, int nreq)
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{
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return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
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wr->send_flags & IB_SEND_SIGNALED,
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wr->send_flags & IB_SEND_SOLICITED);
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return mlx5r_begin_wqe(qp, seg, ctrl, idx, size, cur_edge, nreq,
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send_ieth(wr), wr->send_flags & IB_SEND_SIGNALED,
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wr->send_flags & IB_SEND_SOLICITED);
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}
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static void finish_wqe(struct mlx5_ib_qp *qp,
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struct mlx5_wqe_ctrl_seg *ctrl,
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void *seg, u8 size, void *cur_edge,
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unsigned int idx, u64 wr_id, int nreq, u8 fence,
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u32 mlx5_opcode)
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void mlx5r_finish_wqe(struct mlx5_ib_qp *qp, struct mlx5_wqe_ctrl_seg *ctrl,
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void *seg, u8 size, void *cur_edge, unsigned int idx,
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u64 wr_id, int nreq, u8 fence, u32 mlx5_opcode)
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{
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u8 opmod = 0;
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@ -912,8 +858,8 @@ static int handle_psv(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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/*
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* SET_PSV WQEs are not signaled and solicited on error.
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*/
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err = __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
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false, true);
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err = mlx5r_begin_wqe(qp, seg, ctrl, idx, size, cur_edge, nreq,
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send_ieth(wr), false, true);
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if (unlikely(err)) {
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mlx5_ib_warn(dev, "\n");
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err = -ENOMEM;
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@ -924,8 +870,8 @@ static int handle_psv(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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mlx5_ib_warn(dev, "\n");
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goto out;
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}
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finish_wqe(qp, *ctrl, *seg, *size, *cur_edge, *idx, wr->wr_id, nreq,
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next_fence, MLX5_OPCODE_SET_PSV);
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mlx5r_finish_wqe(qp, *ctrl, *seg, *size, *cur_edge, *idx, wr->wr_id,
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nreq, next_fence, MLX5_OPCODE_SET_PSV);
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out:
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return err;
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@ -965,8 +911,8 @@ static int handle_reg_mr_integrity(struct mlx5_ib_dev *dev,
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if (unlikely(err))
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goto out;
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finish_wqe(qp, *ctrl, *seg, *size, *cur_edge, *idx, wr->wr_id,
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nreq, fence, MLX5_OPCODE_UMR);
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mlx5r_finish_wqe(qp, *ctrl, *seg, *size, *cur_edge, *idx,
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wr->wr_id, nreq, fence, MLX5_OPCODE_UMR);
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err = begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq);
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if (unlikely(err)) {
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@ -997,8 +943,8 @@ static int handle_reg_mr_integrity(struct mlx5_ib_dev *dev,
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mlx5_ib_warn(dev, "\n");
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goto out;
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}
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finish_wqe(qp, *ctrl, *seg, *size, *cur_edge, *idx, wr->wr_id, nreq,
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fence, MLX5_OPCODE_UMR);
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mlx5r_finish_wqe(qp, *ctrl, *seg, *size, *cur_edge, *idx, wr->wr_id,
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nreq, fence, MLX5_OPCODE_UMR);
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sig_attrs = mr->ibmr.sig_attrs;
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err = handle_psv(dev, qp, wr, ctrl, seg, size, cur_edge, idx, nreq,
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@ -1142,6 +1088,32 @@ out:
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return err;
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}
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void mlx5r_ring_db(struct mlx5_ib_qp *qp, unsigned int nreq,
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struct mlx5_wqe_ctrl_seg *ctrl)
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{
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struct mlx5_bf *bf = &qp->bf;
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qp->sq.head += nreq;
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/* Make sure that descriptors are written before
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* updating doorbell record and ringing the doorbell
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*/
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wmb();
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qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
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/* Make sure doorbell record is visible to the HCA before
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* we hit doorbell.
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*/
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wmb();
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mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset);
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/* Make sure doorbells don't leak out of SQ spinlock
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* and reach the HCA out of order.
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*/
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bf->offset ^= bf->buf_size;
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}
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int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
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const struct ib_send_wr **bad_wr, bool drain)
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{
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@ -1150,7 +1122,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
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struct mlx5_core_dev *mdev = dev->mdev;
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struct mlx5_ib_qp *qp = to_mqp(ibqp);
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struct mlx5_wqe_xrc_seg *xrc;
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struct mlx5_bf *bf;
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void *cur_edge;
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int size;
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unsigned long flags;
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@ -1172,8 +1143,6 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
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if (qp->type == IB_QPT_GSI)
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return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
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bf = &qp->bf;
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spin_lock_irqsave(&qp->sq.lock, flags);
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for (nreq = 0; wr; nreq++, wr = wr->next) {
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@ -1285,35 +1254,16 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
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}
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qp->next_fence = next_fence;
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finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
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fence, mlx5_ib_opcode[wr->opcode]);
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mlx5r_finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id,
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nreq, fence, mlx5_ib_opcode[wr->opcode]);
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skip_psv:
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if (0)
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dump_wqe(qp, idx, size);
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}
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out:
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if (likely(nreq)) {
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qp->sq.head += nreq;
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/* Make sure that descriptors are written before
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* updating doorbell record and ringing the doorbell
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*/
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wmb();
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qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
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/* Make sure doorbell record is visible to the HCA before
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* we hit doorbell.
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*/
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wmb();
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mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset);
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/* Make sure doorbells don't leak out of SQ spinlock
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* and reach the HCA out of order.
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*/
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bf->offset ^= bf->buf_size;
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}
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if (likely(nreq))
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mlx5r_ring_db(qp, nreq, ctrl);
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spin_unlock_irqrestore(&qp->sq.lock, flags);
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@ -1353,7 +1303,7 @@ int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
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ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
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for (nreq = 0; wr; nreq++, wr = wr->next) {
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if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
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if (mlx5r_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
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err = -ENOMEM;
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*bad_wr = wr;
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goto out;
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@ -41,6 +41,66 @@ static inline void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
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return fragment_end + MLX5_SEND_WQE_BB;
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}
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/* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
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* next nearby edge and get new address translation for current WQE position.
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* @sq: SQ buffer.
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* @seg: Current WQE position (16B aligned).
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* @wqe_sz: Total current WQE size [16B].
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* @cur_edge: Updated current edge.
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*/
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static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
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u32 wqe_sz, void **cur_edge)
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{
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u32 idx;
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if (likely(*seg != *cur_edge))
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return;
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idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
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*cur_edge = get_sq_edge(sq, idx);
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*seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
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}
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/* mlx5r_memcpy_send_wqe - copy data from src to WQE and update the relevant
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* WQ's pointers. At the end @seg is aligned to 16B regardless the copied size.
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* @sq: SQ buffer.
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* @cur_edge: Updated current edge.
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* @seg: Current WQE position (16B aligned).
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* @wqe_sz: Total current WQE size [16B].
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* @src: Pointer to copy from.
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* @n: Number of bytes to copy.
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*/
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static inline void mlx5r_memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
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void **seg, u32 *wqe_sz,
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const void *src, size_t n)
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{
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while (likely(n)) {
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size_t leftlen = *cur_edge - *seg;
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size_t copysz = min_t(size_t, leftlen, n);
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size_t stride;
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memcpy(*seg, src, copysz);
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n -= copysz;
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src += copysz;
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stride = !n ? ALIGN(copysz, 16) : copysz;
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*seg += stride;
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*wqe_sz += stride >> 4;
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handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
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}
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}
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int mlx5r_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq);
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int mlx5r_begin_wqe(struct mlx5_ib_qp *qp, void **seg,
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struct mlx5_wqe_ctrl_seg **ctrl, unsigned int *idx,
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int *size, void **cur_edge, int nreq, __be32 general_id,
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bool send_signaled, bool solicited);
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void mlx5r_finish_wqe(struct mlx5_ib_qp *qp, struct mlx5_wqe_ctrl_seg *ctrl,
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void *seg, u8 size, void *cur_edge, unsigned int idx,
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u64 wr_id, int nreq, u8 fence, u32 mlx5_opcode);
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void mlx5r_ring_db(struct mlx5_ib_qp *qp, unsigned int nreq,
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struct mlx5_wqe_ctrl_seg *ctrl);
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int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
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const struct ib_send_wr **bad_wr, bool drain);
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int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
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