ARM: 9274/1: Add hwcap for Speculative Store Bypassing Safe
Speculative Store Bypassing Safe(FEAT_SSBS) is a feature present in AArch32 state for Armv8 and is represented by ID_PFR2_EL1.SSBS identification register. This feature denotes the presence of PSTATE.ssbs bit and hence adding a hwcap will enable the userspace to check it before trying to set/unset this PSTATE. This commit adds the ID feature bit detection, and uses elf_hwcap2 accordingly. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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@ -44,5 +44,6 @@
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#define HWCAP2_SHA2 (1 << 3)
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#define HWCAP2_CRC32 (1 << 4)
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#define HWCAP2_SB (1 << 5)
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#define HWCAP2_SSBS (1 << 6)
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#endif /* _UAPI__ASMARM_HWCAP_H */
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@ -451,6 +451,7 @@ static void __init cpuid_init_hwcaps(void)
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int block;
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u32 isar5;
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u32 isar6;
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u32 pfr2;
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if (cpu_architecture() < CPU_ARCH_ARMv7)
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return;
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@ -492,6 +493,12 @@ static void __init cpuid_init_hwcaps(void)
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block = cpuid_feature_extract_field(isar6, 12);
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if (block >= 1)
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elf_hwcap2 |= HWCAP2_SB;
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/* Check for Speculative Store Bypassing control */
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pfr2 = read_cpuid_ext(CPUID_EXT_PFR2);
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block = cpuid_feature_extract_field(pfr2, 4);
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if (block >= 1)
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elf_hwcap2 |= HWCAP2_SSBS;
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}
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static void __init elf_hwcap_fixup(void)
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@ -1272,6 +1279,7 @@ static const char *hwcap2_str[] = {
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"sha2",
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"crc32",
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"sb",
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"ssbs",
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NULL
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};
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