clk: divider: Add support for specifying parents via DT/pointers
After commit fc0c209c14 ("clk: Allow parents to be specified without
string names") we can use DT or direct clk_hw pointers to specify
parents. Create a generic function that shouldn't be used very often to
encode the multitude of ways of registering a divider clk with different
parent information. Then add a bunch of wrapper macros that only pass
down what needs to be passed down to the generic function to support
this with less arguments.
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-13-sboyd@kernel.org
[sboyd@kernel.org: Export __clk_hw_register_divider]
This commit is contained in:
Stephen Boyd
parent
194efb6e26
commit
ff25881713
@ -463,11 +463,12 @@ const struct clk_ops clk_divider_ro_ops = {
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};
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EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
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static struct clk_hw *_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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spinlock_t *lock)
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struct clk_hw *__clk_hw_register_divider(struct device *dev,
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struct device_node *np, const char *name,
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const char *parent_name, const struct clk_hw *parent_hw,
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const struct clk_parent_data *parent_data, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
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const struct clk_div_table *table, spinlock_t *lock)
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{
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struct clk_divider *div;
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struct clk_hw *hw;
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@ -514,55 +515,7 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
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return hw;
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}
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/**
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* clk_register_divider - register a divider clock with the clock framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_name: name of clock's parent
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @lock: shared register lock for this clock
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*/
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struct clk *clk_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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struct clk_hw *hw;
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hw = _register_divider(dev, name, parent_name, flags, reg, shift,
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width, clk_divider_flags, NULL, lock);
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if (IS_ERR(hw))
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return ERR_CAST(hw);
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return hw->clk;
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}
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EXPORT_SYMBOL_GPL(clk_register_divider);
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/**
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* clk_hw_register_divider - register a divider clock with the clock framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_name: name of clock's parent
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @lock: shared register lock for this clock
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*/
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struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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return _register_divider(dev, name, parent_name, flags, reg, shift,
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width, clk_divider_flags, NULL, lock);
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}
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EXPORT_SYMBOL_GPL(clk_hw_register_divider);
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EXPORT_SYMBOL_GPL(__clk_hw_register_divider);
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/**
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* clk_register_divider_table - register a table based divider clock with
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@ -586,39 +539,15 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
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{
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struct clk_hw *hw;
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hw = _register_divider(dev, name, parent_name, flags, reg, shift,
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width, clk_divider_flags, table, lock);
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hw = __clk_hw_register_divider(dev, NULL, name, parent_name, NULL,
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NULL, flags, reg, shift, width, clk_divider_flags,
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table, lock);
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if (IS_ERR(hw))
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return ERR_CAST(hw);
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return hw->clk;
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}
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EXPORT_SYMBOL_GPL(clk_register_divider_table);
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/**
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* clk_hw_register_divider_table - register a table based divider clock with
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* the clock framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_name: name of clock's parent
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @table: array of divider/value pairs ending with a div set to 0
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* @lock: shared register lock for this clock
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*/
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struct clk_hw *clk_hw_register_divider_table(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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spinlock_t *lock)
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{
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return _register_divider(dev, name, parent_name, flags, reg, shift,
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width, clk_divider_flags, table, lock);
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}
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EXPORT_SYMBOL_GPL(clk_hw_register_divider_table);
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void clk_unregister_divider(struct clk *clk)
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{
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struct clk_divider *div;
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@ -626,24 +626,153 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
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const struct clk_div_table *table, u8 width,
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unsigned long flags);
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struct clk *clk_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, spinlock_t *lock);
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struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, spinlock_t *lock);
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struct clk_hw *__clk_hw_register_divider(struct device *dev,
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struct device_node *np, const char *name,
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const char *parent_name, const struct clk_hw *parent_hw,
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const struct clk_parent_data *parent_data, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
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const struct clk_div_table *table, spinlock_t *lock);
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struct clk *clk_register_divider_table(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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spinlock_t *lock);
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struct clk_hw *clk_hw_register_divider_table(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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spinlock_t *lock);
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/**
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* clk_register_divider - register a divider clock with the clock framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_name: name of clock's parent
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @lock: shared register lock for this clock
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*/
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#define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
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clk_divider_flags, lock) \
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clk_register_divider_table((dev), (name), (parent_name), (flags), \
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(reg), (shift), (width), \
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(clk_divider_flags), NULL, (lock))
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/**
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* clk_hw_register_divider - register a divider clock with the clock framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_name: name of clock's parent
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @lock: shared register lock for this clock
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*/
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#define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
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width, clk_divider_flags, lock) \
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__clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
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NULL, (flags), (reg), (shift), (width), \
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(clk_divider_flags), NULL, (lock))
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/**
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* clk_hw_register_divider_parent_hw - register a divider clock with the clock
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* framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_hw: pointer to parent clk
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @lock: shared register lock for this clock
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*/
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#define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
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shift, width, clk_divider_flags, \
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lock) \
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__clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
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NULL, (flags), (reg), (shift), (width), \
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(clk_divider_flags), NULL, (lock))
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/**
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* clk_hw_register_divider_parent_data - register a divider clock with the clock
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* framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_data: parent clk data
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @lock: shared register lock for this clock
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*/
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#define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
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reg, shift, width, \
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clk_divider_flags, lock) \
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__clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
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(parent_data), (flags), (reg), (shift), \
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(width), (clk_divider_flags), NULL, (lock))
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/**
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* clk_hw_register_divider_table - register a table based divider clock with
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* the clock framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_name: name of clock's parent
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @table: array of divider/value pairs ending with a div set to 0
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* @lock: shared register lock for this clock
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*/
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#define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
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shift, width, clk_divider_flags, table, \
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lock) \
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__clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
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NULL, (flags), (reg), (shift), (width), \
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(clk_divider_flags), (table), (lock))
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/**
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* clk_hw_register_divider_table_parent_hw - register a table based divider
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* clock with the clock framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_hw: pointer to parent clk
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @table: array of divider/value pairs ending with a div set to 0
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* @lock: shared register lock for this clock
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*/
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#define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
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reg, shift, width, \
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clk_divider_flags, table, \
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lock) \
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__clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
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NULL, (flags), (reg), (shift), (width), \
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(clk_divider_flags), (table), (lock))
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/**
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* clk_hw_register_divider_table_parent_data - register a table based divider
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* clock with the clock framework
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* @dev: device registering this clock
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* @name: name of this clock
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* @parent_data: parent clk data
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* @flags: framework-specific flags
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* @reg: register address to adjust divider
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* @shift: number of bits to shift the bitfield
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* @width: width of the bitfield
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* @clk_divider_flags: divider-specific flags for this clock
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* @table: array of divider/value pairs ending with a div set to 0
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* @lock: shared register lock for this clock
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*/
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#define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
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flags, reg, shift, width, \
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clk_divider_flags, table, \
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lock) \
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__clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
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(parent_data), (flags), (reg), (shift), \
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(width), (clk_divider_flags), (table), \
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(lock))
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void clk_unregister_divider(struct clk *clk);
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void clk_hw_unregister_divider(struct clk_hw *hw);
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