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media: ccs-pll: Fix link frequency for C-PHY

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The highest fundamental frequency signal for C-PHY is half of the symbol
rate which is similar to D-PHY. Take this into account in ccs-pll.

Also remove the outdated comment.

Fixes: 8030aa4f9c ("media: ccs-pll: Add C-PHY support")
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Sakari Ailus 2020-12-11 23:21:28 +01:00 committed by Mauro Carvalho Chehab
parent 896111dc4b
commit ff474acc4b
1 changed files with 1 additions and 7 deletions
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8
drivers/media/i2c/ccs-pll.c
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@ -772,14 +772,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
switch (pll->bus_type) {
case CCS_PLL_BUS_TYPE_CSI2_DPHY:
/* CSI transfers 2 bits per clock per lane; thus times 2 */
op_sys_clk_freq_hz_sdr = pll->link_freq * 2
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
1 : pll->csi2.lanes);
break;
case CCS_PLL_BUS_TYPE_CSI2_CPHY:
op_sys_clk_freq_hz_sdr =
pll->link_freq
op_sys_clk_freq_hz_sdr = pll->link_freq * 2
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
1 : pll->csi2.lanes);
break;