drm/msm/dsi: Populate the 10nm PHY funcs
Populate the PHY ops with the downstream driver as reference. There are a couple of TODOs which need to be resolved: - The PHY timings are all hardcoded for now. This needs to be replaced with automatic calculations once we get/understand them. - There are some lane configuration registers which use a new representation between physical and logical lane mappings. For now, we've hardcoced them to follow the default mapping (i.e logical 0 -> phy 0, logical 1 -> phy 1 etc). Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Archit Taneja
Rob Clark
parent
28e4309ab9
commit
ff73ff1940
@ -8,9 +8,208 @@
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#include "dsi_phy.h"
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#include "dsi.xml.h"
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static int dsi_phy_hw_v3_0_is_pll_on(struct msm_dsi_phy *phy)
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{
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void __iomem *base = phy->base;
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u32 data = 0;
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data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
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mb(); /* make sure read happened */
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return (data & BIT(0));
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}
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static void dsi_phy_hw_v3_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable)
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{
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void __iomem *lane_base = phy->lane_base;
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int phy_lane_0 = 0; /* TODO: Support all lane swap configs */
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/*
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* LPRX and CDRX need to enabled only for physical data lane
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* corresponding to the logical data lane 0
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*/
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if (enable)
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dsi_phy_write(lane_base +
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REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3);
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else
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dsi_phy_write(lane_base +
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REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0);
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}
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static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
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{
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int i;
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u8 tx_dctrl[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };
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void __iomem *lane_base = phy->lane_base;
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/* Strength ctrl settings */
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for (i = 0; i < 5; i++) {
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dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i),
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0x55);
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/*
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* Disable LPRX and CDRX for all lanes. And later on, it will
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* be only enabled for the physical data lane corresponding
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* to the logical data lane 0
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*/
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dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i), 0);
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dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i), 0x0);
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dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(i),
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0x88);
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}
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dsi_phy_hw_v3_0_config_lpcdrx(phy, true);
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/* other settings */
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for (i = 0; i < 5; i++) {
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dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG0(i), 0x0);
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dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG1(i), 0x0);
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dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG2(i), 0x0);
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dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG3(i),
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i == 4 ? 0x80 : 0x0);
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dsi_phy_write(lane_base +
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REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(i), 0x0);
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dsi_phy_write(lane_base +
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REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(i), 0x0);
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dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(i),
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tx_dctrl[i]);
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}
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/* Toggle BIT 0 to release freeze I/0 */
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dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05);
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dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);
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}
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static int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
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struct msm_dsi_phy_clk_request *clk_req)
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{
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/*
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* TODO: These params need to be computed, they're currently hardcoded
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* for a 1440x2560@60Hz panel with a byteclk of 100.618 Mhz, and a
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* default escape clock of 19.2 Mhz.
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*/
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timing->hs_halfbyte_en = 0;
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timing->clk_zero = 0x1c;
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timing->clk_prepare = 0x07;
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timing->clk_trail = 0x07;
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timing->hs_exit = 0x23;
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timing->hs_zero = 0x21;
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timing->hs_prepare = 0x07;
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timing->hs_trail = 0x07;
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timing->hs_rqst = 0x05;
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timing->ta_sure = 0x00;
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timing->ta_go = 0x03;
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timing->ta_get = 0x04;
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timing->shared_timings.clk_pre = 0x2d;
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timing->shared_timings.clk_post = 0x0d;
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return 0;
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}
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static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
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struct msm_dsi_phy_clk_request *clk_req)
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{
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int ret;
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u32 status;
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u32 const delay_us = 5;
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u32 const timeout_us = 1000;
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struct msm_dsi_dphy_timing *timing = &phy->timing;
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void __iomem *base = phy->base;
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u32 data;
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DBG("");
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if (msm_dsi_dphy_timing_calc_v3(timing, clk_req)) {
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dev_err(&phy->pdev->dev,
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"%s: D-PHY timing calculation failed\n", __func__);
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return -EINVAL;
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}
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if (dsi_phy_hw_v3_0_is_pll_on(phy))
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pr_warn("PLL turned on before configuring PHY\n");
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/* wait for REFGEN READY */
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ret = readl_poll_timeout_atomic(base + REG_DSI_10nm_PHY_CMN_PHY_STATUS,
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status, (status & BIT(0)),
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delay_us, timeout_us);
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if (ret) {
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pr_err("Ref gen not ready. Aborting\n");
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return -EINVAL;
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}
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/* de-assert digital and pll power down */
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data = BIT(6) | BIT(5);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data);
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/* Assert PLL core reset */
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0x00);
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/* turn off resync FIFO */
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x00);
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/* Select MS1 byte-clk */
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_GLBL_CTRL, 0x10);
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/* Enable LDO */
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_VREG_CTRL, 0x59);
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/* Configure PHY lane swap (TODO: we need to calculate this) */
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG0, 0x21);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG1, 0x84);
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/* DSI PHY timings */
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0,
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timing->hs_halfbyte_en);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1,
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timing->clk_zero);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2,
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timing->clk_prepare);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3,
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timing->clk_trail);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4,
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timing->hs_exit);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5,
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timing->hs_zero);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6,
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timing->hs_prepare);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7,
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timing->hs_trail);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8,
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timing->hs_rqst);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9,
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timing->ta_go | (timing->ta_sure << 3));
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10,
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timing->ta_get);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11,
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0x00);
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/* Remove power down from all blocks */
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, 0x7f);
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/* power up lanes */
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data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_CTRL_0);
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/* TODO: only power up lanes that are used */
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data |= 0x1F;
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data);
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0, 0x1F);
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/* Select full-rate mode */
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dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40);
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ret = msm_dsi_pll_set_usecase(phy->pll, phy->usecase);
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if (ret) {
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dev_err(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
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__func__, ret);
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return ret;
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}
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/* DSI lane settings */
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dsi_phy_hw_v3_0_lane_settings(phy);
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DBG("DSI%d PHY enabled", phy->id);
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return 0;
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}
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