ath9k_hw: Handle AR_INTR_SYNC_HOST1_(FATAL|PERR) on AR9003
Interrupts with the sync_cause AR_INTR_SYNC_HOST1_FATAL and AR_INTR_SYNC_HOST1_PERR have to be handled using a chip reset. Otherwise a interrupt storm with unhandled interrupts will cause a hang or crash of the machine. Signed-off-by: Sven Eckelmann <sven@narfation.org> Signed-off-by: Simon Wunderlich <siwu@hrz.tu-chemnitz.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -182,6 +182,7 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
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struct ath9k_hw_capabilities *pCap = &ah->caps;
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struct ath_common *common = ath9k_hw_common(ah);
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u32 sync_cause = 0, async_cause, async_mask = AR_INTR_MAC_IRQ;
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bool fatal_int;
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if (ath9k_hw_mci_is_enabled(ah))
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async_mask |= AR_INTR_ASYNC_MASK_MCI;
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@ -310,6 +311,22 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
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if (sync_cause) {
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ath9k_debug_sync_cause(common, sync_cause);
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fatal_int =
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(sync_cause &
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(AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
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? true : false;
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if (fatal_int) {
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if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
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ath_dbg(common, ANY,
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"received PCI FATAL interrupt\n");
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}
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if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
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ath_dbg(common, ANY,
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"received PCI PERR interrupt\n");
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}
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*masked |= ATH9K_INT_FATAL;
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}
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if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
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REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
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