perf/x86/intel: Extend the ref-cycles event to GP counters
The current ref-cycles event is only available on the fixed counter 2. Starting from the GLC and GRT core, the architectural UnHalted Reference Cycles event (0x013c) which is available on general-purpose counters can collect the exact same events as the fixed counter 2. Update the mapping of ref-cycles to 0x013c. So the ref-cycles can be available on both fixed counter 2 and general-purpose counters. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20230911144139.2354015-1-kan.liang@linux.intel.com
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@ -211,6 +211,14 @@ static struct event_constraint intel_slm_event_constraints[] __read_mostly =
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
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FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint intel_skl_event_constraints[] = {
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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@ -314,6 +322,7 @@ static struct event_constraint intel_glc_event_constraints[] = {
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FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
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FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
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METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
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METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
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@ -5983,6 +5992,12 @@ static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)
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return 0;
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}
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static __always_inline void intel_pmu_ref_cycles_ext(void)
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{
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if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED)))
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intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c;
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}
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static __always_inline void intel_pmu_init_glc(struct pmu *pmu)
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{
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x86_pmu.late_ack = true;
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@ -6005,6 +6020,8 @@ static __always_inline void intel_pmu_init_glc(struct pmu *pmu)
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memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
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hybrid(pmu, event_constraints) = intel_glc_event_constraints;
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hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;
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intel_pmu_ref_cycles_ext();
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}
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static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
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@ -6021,9 +6038,11 @@ static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
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memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
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hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
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hybrid(pmu, event_constraints) = intel_slm_event_constraints;
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hybrid(pmu, event_constraints) = intel_grt_event_constraints;
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hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;
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hybrid(pmu, extra_regs) = intel_grt_extra_regs;
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intel_pmu_ref_cycles_ext();
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}
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__init int intel_pmu_init(void)
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