drivers/video/acornfb.c: remove dead code
acornfb checks for HAS_VIDC while support for that macro was removed in v2.6.23 (when the arm26 port was removed). So we can remove a bit of dead code. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Paul Bolle
Linus Torvalds
parent
40a0d32d1e
commit
ffd29195ed
@ -37,14 +37,6 @@
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#include "acornfb.h"
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/*
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* VIDC machines can't do 16 or 32BPP modes.
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*/
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#ifdef HAS_VIDC
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#undef FBCON_HAS_CFB16
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#undef FBCON_HAS_CFB32
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#endif
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/*
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* Default resolution.
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* NOTE that it has to be supported in the table towards
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@ -106,238 +98,6 @@ static struct vidc_timing current_vidc;
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extern unsigned int vram_size; /* set by setup.c */
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#ifdef HAS_VIDC
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#define MAX_SIZE 480*1024
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/* CTL VIDC Actual
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* 24.000 0 8.000
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* 25.175 0 8.392
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* 36.000 0 12.000
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* 24.000 1 12.000
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* 25.175 1 12.588
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* 24.000 2 16.000
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* 25.175 2 16.783
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* 36.000 1 18.000
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* 24.000 3 24.000
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* 36.000 2 24.000
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* 25.175 3 25.175
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* 36.000 3 36.000
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*/
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struct pixclock {
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u_long min_clock;
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u_long max_clock;
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u_int vidc_ctl;
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u_int vid_ctl;
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};
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static struct pixclock arc_clocks[] = {
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/* we allow +/-1% on these */
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{ 123750, 126250, VIDC_CTRL_DIV3, VID_CTL_24MHz }, /* 8.000MHz */
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{ 82500, 84167, VIDC_CTRL_DIV2, VID_CTL_24MHz }, /* 12.000MHz */
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{ 61875, 63125, VIDC_CTRL_DIV1_5, VID_CTL_24MHz }, /* 16.000MHz */
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{ 41250, 42083, VIDC_CTRL_DIV1, VID_CTL_24MHz }, /* 24.000MHz */
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};
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static struct pixclock *
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acornfb_valid_pixrate(struct fb_var_screeninfo *var)
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{
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u_long pixclock = var->pixclock;
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u_int i;
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if (!var->pixclock)
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return NULL;
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for (i = 0; i < ARRAY_SIZE(arc_clocks); i++)
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if (pixclock > arc_clocks[i].min_clock &&
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pixclock < arc_clocks[i].max_clock)
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return arc_clocks + i;
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return NULL;
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}
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/* VIDC Rules:
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* hcr : must be even (interlace, hcr/2 must be even)
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* hswr : must be even
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* hdsr : must be odd
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* hder : must be odd
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*
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* vcr : must be odd
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* vswr : >= 1
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* vdsr : >= 1
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* vder : >= vdsr
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* if interlaced, then hcr/2 must be even
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*/
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static void
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acornfb_set_timing(struct fb_var_screeninfo *var)
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{
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struct pixclock *pclk;
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struct vidc_timing vidc;
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u_int horiz_correction;
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u_int sync_len, display_start, display_end, cycle;
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u_int is_interlaced;
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u_int vid_ctl, vidc_ctl;
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u_int bandwidth;
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memset(&vidc, 0, sizeof(vidc));
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pclk = acornfb_valid_pixrate(var);
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vidc_ctl = pclk->vidc_ctl;
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vid_ctl = pclk->vid_ctl;
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bandwidth = var->pixclock * 8 / var->bits_per_pixel;
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/* 25.175, 4bpp = 79.444ns per byte, 317.776ns per word: fifo = 2,6 */
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if (bandwidth > 143500)
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vidc_ctl |= VIDC_CTRL_FIFO_3_7;
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else if (bandwidth > 71750)
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vidc_ctl |= VIDC_CTRL_FIFO_2_6;
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else if (bandwidth > 35875)
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vidc_ctl |= VIDC_CTRL_FIFO_1_5;
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else
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vidc_ctl |= VIDC_CTRL_FIFO_0_4;
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switch (var->bits_per_pixel) {
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case 1:
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horiz_correction = 19;
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vidc_ctl |= VIDC_CTRL_1BPP;
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break;
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case 2:
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horiz_correction = 11;
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vidc_ctl |= VIDC_CTRL_2BPP;
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break;
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case 4:
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horiz_correction = 7;
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vidc_ctl |= VIDC_CTRL_4BPP;
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break;
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default:
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case 8:
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horiz_correction = 5;
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vidc_ctl |= VIDC_CTRL_8BPP;
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break;
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}
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if (var->sync & FB_SYNC_COMP_HIGH_ACT) /* should be FB_SYNC_COMP */
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vidc_ctl |= VIDC_CTRL_CSYNC;
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else {
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if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
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vid_ctl |= VID_CTL_HS_NHSYNC;
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if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
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vid_ctl |= VID_CTL_VS_NVSYNC;
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}
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sync_len = var->hsync_len;
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display_start = sync_len + var->left_margin;
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display_end = display_start + var->xres;
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cycle = display_end + var->right_margin;
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/* if interlaced, then hcr/2 must be even */
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is_interlaced = (var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED;
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if (is_interlaced) {
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vidc_ctl |= VIDC_CTRL_INTERLACE;
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if (cycle & 2) {
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cycle += 2;
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var->right_margin += 2;
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}
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}
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vidc.h_cycle = (cycle - 2) / 2;
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vidc.h_sync_width = (sync_len - 2) / 2;
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vidc.h_border_start = (display_start - 1) / 2;
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vidc.h_display_start = (display_start - horiz_correction) / 2;
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vidc.h_display_end = (display_end - horiz_correction) / 2;
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vidc.h_border_end = (display_end - 1) / 2;
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vidc.h_interlace = (vidc.h_cycle + 1) / 2;
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sync_len = var->vsync_len;
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display_start = sync_len + var->upper_margin;
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display_end = display_start + var->yres;
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cycle = display_end + var->lower_margin;
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if (is_interlaced)
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cycle = (cycle - 3) / 2;
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else
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cycle = cycle - 1;
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vidc.v_cycle = cycle;
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vidc.v_sync_width = sync_len - 1;
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vidc.v_border_start = display_start - 1;
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vidc.v_display_start = vidc.v_border_start;
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vidc.v_display_end = display_end - 1;
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vidc.v_border_end = vidc.v_display_end;
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if (machine_is_a5k())
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__raw_writeb(vid_ctl, IOEB_VID_CTL);
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if (memcmp(¤t_vidc, &vidc, sizeof(vidc))) {
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current_vidc = vidc;
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vidc_writel(0xe0000000 | vidc_ctl);
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vidc_writel(0x80000000 | (vidc.h_cycle << 14));
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vidc_writel(0x84000000 | (vidc.h_sync_width << 14));
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vidc_writel(0x88000000 | (vidc.h_border_start << 14));
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vidc_writel(0x8c000000 | (vidc.h_display_start << 14));
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vidc_writel(0x90000000 | (vidc.h_display_end << 14));
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vidc_writel(0x94000000 | (vidc.h_border_end << 14));
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vidc_writel(0x98000000);
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vidc_writel(0x9c000000 | (vidc.h_interlace << 14));
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vidc_writel(0xa0000000 | (vidc.v_cycle << 14));
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vidc_writel(0xa4000000 | (vidc.v_sync_width << 14));
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vidc_writel(0xa8000000 | (vidc.v_border_start << 14));
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vidc_writel(0xac000000 | (vidc.v_display_start << 14));
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vidc_writel(0xb0000000 | (vidc.v_display_end << 14));
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vidc_writel(0xb4000000 | (vidc.v_border_end << 14));
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vidc_writel(0xb8000000);
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vidc_writel(0xbc000000);
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}
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#ifdef DEBUG_MODE_SELECTION
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printk(KERN_DEBUG "VIDC registers for %dx%dx%d:\n", var->xres,
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var->yres, var->bits_per_pixel);
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printk(KERN_DEBUG " H-cycle : %d\n", vidc.h_cycle);
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printk(KERN_DEBUG " H-sync-width : %d\n", vidc.h_sync_width);
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printk(KERN_DEBUG " H-border-start : %d\n", vidc.h_border_start);
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printk(KERN_DEBUG " H-display-start : %d\n", vidc.h_display_start);
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printk(KERN_DEBUG " H-display-end : %d\n", vidc.h_display_end);
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printk(KERN_DEBUG " H-border-end : %d\n", vidc.h_border_end);
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printk(KERN_DEBUG " H-interlace : %d\n", vidc.h_interlace);
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printk(KERN_DEBUG " V-cycle : %d\n", vidc.v_cycle);
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printk(KERN_DEBUG " V-sync-width : %d\n", vidc.v_sync_width);
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printk(KERN_DEBUG " V-border-start : %d\n", vidc.v_border_start);
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printk(KERN_DEBUG " V-display-start : %d\n", vidc.v_display_start);
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printk(KERN_DEBUG " V-display-end : %d\n", vidc.v_display_end);
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printk(KERN_DEBUG " V-border-end : %d\n", vidc.v_border_end);
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printk(KERN_DEBUG " VIDC Ctrl (E) : 0x%08X\n", vidc_ctl);
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printk(KERN_DEBUG " IOEB Ctrl : 0x%08X\n", vid_ctl);
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#endif
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}
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static int
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acornfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
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u_int trans, struct fb_info *info)
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{
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union palette pal;
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if (regno >= current_par.palette_size)
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return 1;
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pal.p = 0;
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pal.vidc.reg = regno;
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pal.vidc.red = red >> 12;
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pal.vidc.green = green >> 12;
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pal.vidc.blue = blue >> 12;
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current_par.palette[regno] = pal;
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vidc_writel(pal.p);
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return 0;
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}
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#endif
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#ifdef HAS_VIDC20
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#include <mach/acornfb.h>
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@ -634,16 +394,7 @@ acornfb_adjust_timing(struct fb_info *info, struct fb_var_screeninfo *var, u_int
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/* hsync_len must be even */
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var->hsync_len = (var->hsync_len + 1) & ~1;
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#ifdef HAS_VIDC
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/* left_margin must be odd */
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if ((var->left_margin & 1) == 0) {
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var->left_margin -= 1;
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var->right_margin += 1;
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}
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/* right_margin must be odd */
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var->right_margin |= 1;
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#elif defined(HAS_VIDC20)
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#if defined(HAS_VIDC20)
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/* left_margin must be even */
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if (var->left_margin & 1) {
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var->left_margin += 1;
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@ -787,11 +538,7 @@ static int acornfb_set_par(struct fb_info *info)
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break;
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case 8:
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current_par.palette_size = VIDC_PALETTE_SIZE;
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#ifdef HAS_VIDC
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info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
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#else
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
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#endif
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break;
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#ifdef HAS_VIDC20
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case 16:
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@ -971,9 +718,6 @@ static void acornfb_init_fbinfo(void)
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#if defined(HAS_VIDC20)
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fb_info.var.red.length = 8;
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fb_info.var.transp.length = 4;
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#elif defined(HAS_VIDC)
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fb_info.var.red.length = 4;
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fb_info.var.transp.length = 1;
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#endif
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fb_info.var.green = fb_info.var.red;
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fb_info.var.blue = fb_info.var.red;
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@ -1310,14 +1054,6 @@ static int acornfb_probe(struct platform_device *dev)
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fb_info.fix.smem_start = handle;
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}
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#endif
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#if defined(HAS_VIDC)
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/*
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* Archimedes/A5000 machines use a fixed address for their
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* framebuffers. Free unused pages
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*/
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free_unused_pages(PAGE_OFFSET + size, PAGE_OFFSET + MAX_SIZE);
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#endif
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fb_info.fix.smem_len = size;
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current_par.palette_size = VIDC_PALETTE_SIZE;
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@ -13,10 +13,6 @@
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#include <asm/hardware/iomd.h>
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#define VIDC_PALETTE_SIZE 256
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#define VIDC_NAME "VIDC20"
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#elif defined(HAS_VIDC)
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#include <asm/hardware/memc.h>
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#define VIDC_PALETTE_SIZE 16
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#define VIDC_NAME "VIDC"
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#endif
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#define EXTEND8(x) ((x)|(x)<<8)
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@ -101,31 +97,6 @@ struct modex_params {
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const struct modey_params *modey;
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};
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#ifdef HAS_VIDC
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#define VID_CTL_VS_NVSYNC (1 << 3)
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#define VID_CTL_HS_NHSYNC (1 << 2)
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#define VID_CTL_24MHz (0)
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#define VID_CTL_25MHz (1)
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#define VID_CTL_36MHz (2)
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#define VIDC_CTRL_CSYNC (1 << 7)
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#define VIDC_CTRL_INTERLACE (1 << 6)
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#define VIDC_CTRL_FIFO_0_4 (0 << 4)
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#define VIDC_CTRL_FIFO_1_5 (1 << 4)
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#define VIDC_CTRL_FIFO_2_6 (2 << 4)
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#define VIDC_CTRL_FIFO_3_7 (3 << 4)
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#define VIDC_CTRL_1BPP (0 << 2)
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#define VIDC_CTRL_2BPP (1 << 2)
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#define VIDC_CTRL_4BPP (2 << 2)
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#define VIDC_CTRL_8BPP (3 << 2)
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#define VIDC_CTRL_DIV3 (0 << 0)
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#define VIDC_CTRL_DIV2 (1 << 0)
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#define VIDC_CTRL_DIV1_5 (2 << 0)
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#define VIDC_CTRL_DIV1 (3 << 0)
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#endif
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#ifdef HAS_VIDC20
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/*
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* VIDC20 registers
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