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arm64: dts: qcom: sm8250: add description of dcvsh interrupts

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The change adds SM8250 cpufreq-epss controller interrupts for each
CPU core cluster.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211223075640.2924569-1-vladimir.zapolskiy@linaro.org
This commit is contained in:
Vladimir Zapolskiy 2021-12-23 09:56:40 +02:00 committed by Bjorn Andersson
parent 3b87b01d74
commit ffd6cc92ab
1 changed files with 4 additions and 1 deletions
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5
arch/arm64/boot/dts/qcom/sm8250.dtsi
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@ -4571,7 +4571,10 @@
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
#freq-domain-cells = <1>;
};
};