mt2701:
- add jpeg enconder node mt7623: - refactor dts and add hdmi support -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAl9uCjwXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH5zkg//eBk9qt4UkYFhy1YmG8SMvjPa Qiix0dsalNaxjGodq2z1289qDlkzIXh8rBXKrjy33ILRICyhH4ilnTjpyryeiSJX bviceQO+E29DOwUthnKhM5Aag65SJ62/CVI0v/ofRk+NZD0pwj/RMQBUvpKyVe+1 gdzw76tFm41cIk2vWO5NPVreeediIQVN9oszmUQ6mebA5NA1zk7vyBhOAM5NvWvP jjnMEqRjo1mUYJ/x8QiNDu4shsTRr0vKJGJWUrHq/gAPlQ8xZND5SyChE3CsExM1 5fzpyUdUAqJS6d70RD+ePQ4N8SKxEtIedXk1MoAZBHNP4S2zKtrvGmj6CZ02OisB YlpSQGfkmCYonsnvCpxUuS8mvgtsPkQUx0gtfGOcsQ2DY7ZH/kXaPS8Z35/LgIlW Qhwj9mQ8f6Txr1vzoZsiyRWySdXxo5csOMsis6n0Y9BC6gANOQFRCrHo0yKFDo/3 fBy3XC7U1L2j567GFV85a7MIrsg4OYyb9X2posrWCFunV61R3dU02ZhVlwlEEBs8 uLkhT+lsYKIRI6fhwv9ETBOawCx9iit7BujJjobzsexvQUf/kJ8+EHKucpOqu1Qt P3zObxohYgIlrv4oW6whlmsrKStpNOTzT6OOx1eBX4apU0kZp4opbVV2DWJfsQ4W DlGnwGJF1sUcAkFmb8s= =6jDY -----END PGP SIGNATURE----- Merge tag 'v5.9-next-dts32' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt mt2701: - add jpeg enconder node mt7623: - refactor dts and add hdmi support * tag 'v5.9-next-dts32' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm: dts: mt7623: add missing pause for switchport arm: dts: mt7623: add lima related regulator arm: dts: mt7623: add display subsystem related device nodes arm: dts: mt7623: move display nodes to separate mt7623n.dtsi arm: dts: mt2701: Add jpeg enc device tree node Link: https://lore.kernel.org/r/641d4d47-b7ad-42dd-f7a8-e028a1f64d70@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
fffde96eb0
@ -569,6 +569,19 @@
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<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
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};
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jpegenc: jpegenc@1500a000 {
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compatible = "mediatek,mt2701-jpgenc",
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"mediatek,mtk-jpgenc";
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reg = <0 0x1500a000 0 0x1000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&imgsys CLK_IMG_VENC>;
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clock-names = "jpgenc";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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mediatek,larb = <&larb2>;
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iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
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<&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
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};
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vdecsys: syscon@16000000 {
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compatible = "mediatek,mt2701-vdecsys", "syscon";
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reg = <0 0x16000000 0 0x1000>;
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@ -14,7 +14,6 @@
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#include <dt-bindings/power/mt2701-power.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/memory/mt2701-larb-port.h>
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#include <dt-bindings/reset/mt2701-resets.h>
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#include <dt-bindings/thermal/thermal.h>
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@ -297,17 +296,6 @@
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clock-names = "system-clk", "rtc-clk";
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};
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smi_common: smi@1000c000 {
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compatible = "mediatek,mt7623-smi-common",
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"mediatek,mt2701-smi-common";
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reg = <0 0x1000c000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_SMI>,
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<&mmsys CLK_MM_SMI_COMMON>,
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<&infracfg CLK_INFRA_SMI>;
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clock-names = "apb", "smi", "async";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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pwrap: pwrap@1000d000 {
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compatible = "mediatek,mt7623-pwrap",
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"mediatek,mt2701-pwrap";
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@ -339,17 +327,6 @@
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reg = <0 0x10200100 0 0x1c>;
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};
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iommu: mmsys_iommu@10205000 {
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compatible = "mediatek,mt7623-m4u",
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"mediatek,mt2701-m4u";
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reg = <0 0x10205000 0 0x1000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_M4U>;
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clock-names = "bclk";
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mediatek,larbs = <&larb0 &larb1 &larb2>;
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#iommu-cells = <1>;
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};
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efuse: efuse@10206000 {
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compatible = "mediatek,mt7623-efuse",
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"mediatek,mt8173-efuse";
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@ -725,94 +702,6 @@
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status = "disabled";
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};
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g3dsys: syscon@13000000 {
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compatible = "mediatek,mt7623-g3dsys",
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"mediatek,mt2701-g3dsys",
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"syscon";
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reg = <0 0x13000000 0 0x200>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mali: gpu@13040000 {
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compatible = "mediatek,mt7623-mali", "arm,mali-450";
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reg = <0 0x13040000 0 0x30000>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
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"ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
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"pp";
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clocks = <&topckgen CLK_TOP_MMPLL>,
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<&g3dsys CLK_G3DSYS_CORE>;
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clock-names = "bus", "core";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
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resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
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};
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt7623-mmsys",
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"mediatek,mt2701-mmsys",
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"syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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};
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larb0: larb@14010000 {
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compatible = "mediatek,mt7623-smi-larb",
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"mediatek,mt2701-smi-larb";
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reg = <0 0x14010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <0>;
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clocks = <&mmsys CLK_MM_SMI_LARB0>,
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<&mmsys CLK_MM_SMI_LARB0>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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};
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imgsys: syscon@15000000 {
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compatible = "mediatek,mt7623-imgsys",
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"mediatek,mt2701-imgsys",
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"syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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};
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larb2: larb@15001000 {
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compatible = "mediatek,mt7623-smi-larb",
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"mediatek,mt2701-smi-larb";
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reg = <0 0x15001000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <2>;
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clocks = <&imgsys CLK_IMG_SMI_COMM>,
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<&imgsys CLK_IMG_SMI_COMM>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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};
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jpegdec: jpegdec@15004000 {
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compatible = "mediatek,mt7623-jpgdec",
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"mediatek,mt2701-jpgdec";
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reg = <0 0x15004000 0 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
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<&imgsys CLK_IMG_JPGDEC>;
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clock-names = "jpgdec-smi",
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"jpgdec";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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mediatek,larb = <&larb2>;
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iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
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<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
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};
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vdecsys: syscon@16000000 {
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compatible = "mediatek,mt7623-vdecsys",
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"mediatek,mt2701-vdecsys",
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@ -821,18 +710,6 @@
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#clock-cells = <1>;
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};
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larb1: larb@16010000 {
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compatible = "mediatek,mt7623-smi-larb",
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"mediatek,mt2701-smi-larb";
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reg = <0 0x16010000 0 0x1000>;
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mediatek,smi = <&smi_common>;
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mediatek,larb-id = <1>;
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clocks = <&vdecsys CLK_VDEC_CKGEN>,
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<&vdecsys CLK_VDEC_LARB>;
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clock-names = "apb", "smi";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
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};
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hifsys: syscon@1a000000 {
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compatible = "mediatek,mt7623-hifsys",
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"mediatek,mt2701-hifsys",
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@ -6,7 +6,7 @@
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "mt7623.dtsi"
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#include "mt7623n.dtsi"
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#include "mt6323.dtsi"
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/ {
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@ -21,6 +21,19 @@
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stdout-path = "serial2:115200n8";
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};
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connector {
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compatible = "hdmi-connector";
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label = "hdmi";
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type = "d";
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ddc-i2c-bus = <&hdmiddc0>;
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&hdmi0_out>;
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};
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};
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};
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cpus {
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cpu@0 {
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proc-supply = <&mt6323_vproc_reg>;
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@ -66,6 +79,13 @@
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regulator-always-on;
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};
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reg_vgpu: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vdd_fixed_vgpu";
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regulator-min-microvolt = <1150000>;
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regulator-max-microvolt = <1150000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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@ -114,10 +134,18 @@
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};
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};
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&bls {
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status = "okay";
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};
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&btif {
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status = "okay";
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};
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&cec {
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status = "okay";
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};
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&cir {
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pinctrl-names = "default";
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pinctrl-0 = <&cir_pins_a>;
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@ -128,6 +156,21 @@
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status = "okay";
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};
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&dpi0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpi0_out: endpoint {
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remote-endpoint = <&hdmi0_in>;
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};
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};
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};
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};
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ð {
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status = "okay";
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@ -192,6 +235,7 @@
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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@ -199,6 +243,42 @@
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};
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};
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&hdmi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_pins_a>;
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi0_in: endpoint {
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remote-endpoint = <&dpi0_out>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi0_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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};
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};
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&hdmiddc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_ddc_pins_a>;
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status = "okay";
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};
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&hdmi_phy {
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mediatek,ibias = <0xa>;
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mediatek,ibias_up = <0x1c>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins_a>;
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@ -211,6 +291,11 @@
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status = "okay";
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};
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&mali {
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mali-supply = <®_vgpu>;
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status = "okay";
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};
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&mmc0 {
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_default>;
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@ -330,4 +415,3 @@
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&u3phy2 {
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status = "okay";
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};
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@ -7,7 +7,7 @@
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "mt7623.dtsi"
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#include "mt7623n.dtsi"
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#include "mt6323.dtsi"
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/ {
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@ -24,6 +24,19 @@
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stdout-path = "serial2:115200n8";
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};
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connector {
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compatible = "hdmi-connector";
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label = "hdmi";
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type = "d";
|
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ddc-i2c-bus = <&hdmiddc0>;
|
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|
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port {
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hdmi_connector_in: endpoint {
|
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remote-endpoint = <&hdmi0_out>;
|
||||
};
|
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};
|
||||
};
|
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|
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cpus {
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cpu@0 {
|
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proc-supply = <&mt6323_vproc_reg>;
|
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@ -106,10 +119,18 @@
|
||||
};
|
||||
};
|
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|
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&bls {
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status = "okay";
|
||||
};
|
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|
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&btif {
|
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status = "okay";
|
||||
};
|
||||
|
||||
&cec {
|
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status = "okay";
|
||||
};
|
||||
|
||||
&cir {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cir_pins_a>;
|
||||
@ -120,6 +141,21 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dpi0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
|
||||
@ -203,6 +239,42 @@
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
hdmi0_in: endpoint {
|
||||
remote-endpoint = <&dpi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi_connector_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmiddc0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_ddc_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_phy {
|
||||
mediatek,ibias = <0xa>;
|
||||
mediatek,ibias_up = <0x1c>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_a>;
|
||||
|
||||
306
arch/arm/boot/dts/mt7623n.dtsi
Normal file
306
arch/arm/boot/dts/mt7623n.dtsi
Normal file
@ -0,0 +1,306 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright © 2017-2020 MediaTek Inc.
|
||||
* Author: Sean Wang <sean.wang@mediatek.com>
|
||||
* Ryder Lee <ryder.lee@mediatek.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include "mt7623.dtsi"
|
||||
#include <dt-bindings/memory/mt2701-larb-port.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
rdma0 = &rdma0;
|
||||
rdma1 = &rdma1;
|
||||
};
|
||||
|
||||
g3dsys: syscon@13000000 {
|
||||
compatible = "mediatek,mt7623-g3dsys",
|
||||
"mediatek,mt2701-g3dsys",
|
||||
"syscon";
|
||||
reg = <0 0x13000000 0 0x200>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
mali: gpu@13040000 {
|
||||
compatible = "mediatek,mt7623-mali", "arm,mali-450";
|
||||
reg = <0 0x13040000 0 0x30000>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
|
||||
"ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
|
||||
"pp";
|
||||
clocks = <&topckgen CLK_TOP_MMPLL>,
|
||||
<&g3dsys CLK_G3DSYS_CORE>;
|
||||
clock-names = "bus", "core";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
|
||||
resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
|
||||
};
|
||||
|
||||
mmsys: syscon@14000000 {
|
||||
compatible = "mediatek,mt7623-mmsys",
|
||||
"mediatek,mt2701-mmsys",
|
||||
"syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
larb0: larb@14010000 {
|
||||
compatible = "mediatek,mt7623-smi-larb",
|
||||
"mediatek,mt2701-smi-larb";
|
||||
reg = <0 0x14010000 0 0x1000>;
|
||||
mediatek,smi = <&smi_common>;
|
||||
mediatek,larb-id = <0>;
|
||||
clocks = <&mmsys CLK_MM_SMI_LARB0>,
|
||||
<&mmsys CLK_MM_SMI_LARB0>;
|
||||
clock-names = "apb", "smi";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
|
||||
};
|
||||
|
||||
larb1: larb@16010000 {
|
||||
compatible = "mediatek,mt7623-smi-larb",
|
||||
"mediatek,mt2701-smi-larb";
|
||||
reg = <0 0x16010000 0 0x1000>;
|
||||
mediatek,smi = <&smi_common>;
|
||||
mediatek,larb-id = <1>;
|
||||
clocks = <&vdecsys CLK_VDEC_CKGEN>,
|
||||
<&vdecsys CLK_VDEC_LARB>;
|
||||
clock-names = "apb", "smi";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
|
||||
};
|
||||
|
||||
larb2: larb@15001000 {
|
||||
compatible = "mediatek,mt7623-smi-larb",
|
||||
"mediatek,mt2701-smi-larb";
|
||||
reg = <0 0x15001000 0 0x1000>;
|
||||
mediatek,smi = <&smi_common>;
|
||||
mediatek,larb-id = <2>;
|
||||
clocks = <&imgsys CLK_IMG_SMI_COMM>,
|
||||
<&imgsys CLK_IMG_SMI_COMM>;
|
||||
clock-names = "apb", "smi";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
|
||||
};
|
||||
|
||||
imgsys: syscon@15000000 {
|
||||
compatible = "mediatek,mt7623-imgsys",
|
||||
"mediatek,mt2701-imgsys",
|
||||
"syscon";
|
||||
reg = <0 0x15000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
iommu: mmsys_iommu@10205000 {
|
||||
compatible = "mediatek,mt7623-m4u",
|
||||
"mediatek,mt2701-m4u";
|
||||
reg = <0 0x10205000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infracfg CLK_INFRA_M4U>;
|
||||
clock-names = "bclk";
|
||||
mediatek,larbs = <&larb0 &larb1 &larb2>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
jpegdec: jpegdec@15004000 {
|
||||
compatible = "mediatek,mt7623-jpgdec",
|
||||
"mediatek,mt2701-jpgdec";
|
||||
reg = <0 0x15004000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
|
||||
<&imgsys CLK_IMG_JPGDEC>;
|
||||
clock-names = "jpgdec-smi",
|
||||
"jpgdec";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
|
||||
mediatek,larb = <&larb2>;
|
||||
iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
|
||||
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
|
||||
};
|
||||
|
||||
smi_common: smi@1000c000 {
|
||||
compatible = "mediatek,mt7623-smi-common",
|
||||
"mediatek,mt2701-smi-common";
|
||||
reg = <0 0x1000c000 0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_SMI>,
|
||||
<&mmsys CLK_MM_SMI_COMMON>,
|
||||
<&infracfg CLK_INFRA_SMI>;
|
||||
clock-names = "apb", "smi", "async";
|
||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
|
||||
};
|
||||
|
||||
ovl: ovl@14007000 {
|
||||
compatible = "mediatek,mt7623-disp-ovl",
|
||||
"mediatek,mt2701-disp-ovl";
|
||||
reg = <0 0x14007000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL>;
|
||||
iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
rdma0: rdma@14008000 {
|
||||
compatible = "mediatek,mt7623-disp-rdma",
|
||||
"mediatek,mt2701-disp-rdma";
|
||||
reg = <0 0x14008000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA>;
|
||||
iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
wdma@14009000 {
|
||||
compatible = "mediatek,mt7623-disp-wdma",
|
||||
"mediatek,mt2701-disp-wdma";
|
||||
reg = <0 0x14009000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_DISP_WDMA>;
|
||||
iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
bls: pwm@1400a000 {
|
||||
compatible = "mediatek,mt7623-disp-pwm",
|
||||
"mediatek,mt2701-disp-pwm";
|
||||
reg = <0 0x1400a000 0 0x1000>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&mmsys CLK_MM_MDP_BLS_26M>,
|
||||
<&mmsys CLK_MM_DISP_BLS>;
|
||||
clock-names = "main", "mm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
color: color@1400b000 {
|
||||
compatible = "mediatek,mt7623-disp-color",
|
||||
"mediatek,mt2701-disp-color";
|
||||
reg = <0 0x1400b000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR>;
|
||||
};
|
||||
|
||||
dsi: dsi@1400c000 {
|
||||
compatible = "mediatek,mt7623-dsi",
|
||||
"mediatek,mt2701-dsi";
|
||||
reg = <0 0x1400c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_DSI_ENGINE>,
|
||||
<&mmsys CLK_MM_DSI_DIG>,
|
||||
<&mipi_tx0>;
|
||||
clock-names = "engine", "digital", "hs";
|
||||
phys = <&mipi_tx0>;
|
||||
phy-names = "dphy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mutex: mutex@1400e000 {
|
||||
compatible = "mediatek,mt7623-disp-mutex",
|
||||
"mediatek,mt2701-disp-mutex";
|
||||
reg = <0 0x1400e000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
||||
};
|
||||
|
||||
rdma1: rdma@14012000 {
|
||||
compatible = "mediatek,mt7623-disp-rdma",
|
||||
"mediatek,mt2701-disp-rdma";
|
||||
reg = <0 0x14012000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
|
||||
iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
dpi0: dpi@14014000 {
|
||||
compatible = "mediatek,mt7623-dpi",
|
||||
"mediatek,mt2701-dpi";
|
||||
reg = <0 0x14014000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_DPI1_DIGL>,
|
||||
<&mmsys CLK_MM_DPI1_ENGINE>,
|
||||
<&apmixedsys CLK_APMIXED_TVDPLL>;
|
||||
clock-names = "pixel", "engine", "pll";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hdmi0: hdmi@14015000 {
|
||||
compatible = "mediatek,mt7623-hdmi",
|
||||
"mediatek,mt2701-hdmi";
|
||||
reg = <0 0x14015000 0 0x400>;
|
||||
clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
|
||||
<&mmsys CLK_MM_HDMI_PLL>,
|
||||
<&mmsys CLK_MM_HDMI_AUDIO>,
|
||||
<&mmsys CLK_MM_HDMI_SPDIF>;
|
||||
clock-names = "pixel", "pll", "bclk", "spdif";
|
||||
phys = <&hdmi_phy>;
|
||||
phy-names = "hdmi";
|
||||
mediatek,syscon-hdmi = <&mmsys 0x900>;
|
||||
cec = <&cec>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mipi_tx0: mipi-dphy@10010000 {
|
||||
compatible = "mediatek,mt7623-mipi-tx",
|
||||
"mediatek,mt2701-mipi-tx";
|
||||
reg = <0 0x10010000 0 0x90>;
|
||||
clocks = <&clk26m>;
|
||||
clock-output-names = "mipi_tx0_pll";
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
cec: cec@10012000 {
|
||||
compatible = "mediatek,mt7623-cec",
|
||||
"mediatek,mt8173-cec";
|
||||
reg = <0 0x10012000 0 0xbc>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infracfg CLK_INFRA_CEC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hdmi_phy: phy@10209100 {
|
||||
compatible = "mediatek,mt7623-hdmi-phy",
|
||||
"mediatek,mt2701-hdmi-phy";
|
||||
reg = <0 0x10209100 0 0x24>;
|
||||
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
|
||||
clock-names = "pll_ref";
|
||||
clock-output-names = "hdmitx_dig_cts";
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hdmiddc0: i2c@11013000 {
|
||||
compatible = "mediatek,mt7623-hdmi-ddc",
|
||||
"mediatek,mt8173-hdmi-ddc";
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
|
||||
reg = <0 0x11013000 0 0x1C>;
|
||||
clocks = <&pericfg CLK_PERI_I2C3>;
|
||||
clock-names = "ddc-i2c";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&pio {
|
||||
hdmi_pins_a: hdmi-default {
|
||||
pins-hdmi {
|
||||
pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>;
|
||||
input-enable;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_ddc_pins_a: hdmi_ddc-default {
|
||||
pins-hdmi-ddc {
|
||||
pinmux = <MT7623_PIN_124_GPIO124_FUNC_HDMISCK>,
|
||||
<MT7623_PIN_125_GPIO125_FUNC_HDMISD>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
x
Reference in New Issue
Block a user