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If sg2042_get_pll_ctl_setting() fails then "value" isn't initialized and
it is printed in the debug output. Initialize it to zero.
Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/baf0a490-d5ba-4528-90ba-80399684692d@stanley.mountain
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Clang warns (or errors with CONFIG_WERROR=y):
drivers/clk/sophgo/clk-sg2042-pll.c:396:6: error: variable 'ret' is used uninitialized whenever 'if' condition is true [-Werror,-Wsometimes-uninitialized]
396 | if (sg2042_pll_enable(pll, 0)) {
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/sophgo/clk-sg2042-pll.c:418:9: note: uninitialized use occurs here
418 | return ret;
| ^~~
drivers/clk/sophgo/clk-sg2042-pll.c:396:2: note: remove the 'if' if its condition is always false
396 | if (sg2042_pll_enable(pll, 0)) {
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
397 | pr_warn("Can't disable pll(%s), status error\n", pll->hw.init->name);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
398 | goto out;
| ~~~~~~~~~
399 | }
| ~
drivers/clk/sophgo/clk-sg2042-pll.c:393:9: note: initialize the variable 'ret' to silence this warning
393 | int ret;
| ^
| = 0
1 error generated.
sg2042_pll_enable() only ever returns zero, so this situation cannot
happen, but clang does not perform interprocedural analysis, so it
cannot know this to avoid the warning. Make it clearer to the compiler
by making sg2042_pll_enable() void and eliminate the error handling in
sg2042_clk_pll_set_rate(), which clears up the warning, as ret will
always be initialized.
Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20240710-clk-sg2042-fix-sometimes-uninitialized-pll_set_rate-v1-1-538fa82dd539@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In general it's a good idea to avoid using bare unreachable() because it
introduces undefined behavior in compiled code. but it caused a compilation warning,
Using BUG() instead of unreachable() to resolve compilation warnings.
Fixes the following warnings:
drivers/clk/sophgo/clk-cv18xx-ip.o: warning: objtool: mmux_round_rate() falls through to next function bypass_div_round_rate()
Fixes: 80fd61ec46124 ("clk: sophgo: Add clock support for CV1800 SoC")
Signed-off-by: Li Qiang <liqiang01@kylinos.cn>
Link: https://lore.kernel.org/r/c8e66d51f880127549e2a3e623be6787f62b310d.1720506143.git.liqiang01@kylinos.cn
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
On 32-bit architectures, the 64-bit division leads to a link failure:
arm-linux-gnueabi-ld: drivers/clk/sophgo/clk-cv18xx-pll.o: in function `fpll_calc_rate':
clk-cv18xx-pll.c:(.text.fpll_calc_rate+0x26): undefined reference to `__aeabi_uldivmod'
This one is not called in a fast path, and there is already another div_u64()
variant used in the same function, so convert it to div64_u64_rem().
Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20240415134532.3467817-1-arnd@kernel.org
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202404122344.d5pb2N1I-lkp@intel.com/
Closes: https://lore.kernel.org/oe-kbuild-all/202404140310.QEjZKtTN-lkp@intel.com/
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
