4 Commits

Author	SHA1	Message	Date
David Daney	82622284dd	MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors. ... Processors that support the mips64r2 ISA can in four instructions convert a shifted PGD pointer stored in the upper bits of c0_context into a usable pointer. By doing this we save a memory load and associated potential cache miss in the TLB exception handlers. Since the upper bits of c0_context were holding the CPU number, we move this to the upper bits of c0_xcontext which doesn't have enough bits to hold the PGD pointer, but has plenty for the CPU number. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>	2009-12-17 01:57:01 +00:00
David Daney	362e696428	MIPS: Reorder operations in stackframe.h for better scheduling ... Reorder PT ops to avoid pipeline stalls. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>	2009-12-17 01:56:57 +00:00
David Daney	2a219b0eaa	MIPS: Cavium OCTEON multiplier state preservation. ... For OCTEON, implement a save and restore of the multiplier state across context switches. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>	2009-01-11 09:57:24 +00:00
Ralf Baechle	384740dc49	MIPS: Move headfiles to new location below arch/mips/include ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>	2008-10-11 16:18:52 +01:00