3 Commits

Author	SHA1	Message	Date
Vipul Kumar Samar	1249979242	CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks ... Flag CLK_SET_RATE_PARENT is required for a clock, where we want to propagate clk_set_rate to its parent. This patch adds this to multiple clocks. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com> Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>	2012-11-21 11:45:45 -08:00
Viresh Kumar	10d8935f46	Viresh has moved ... viresh.kumar@st.com email-id doesn't exist anymore as I have left the company. Replace ST's id with viresh.linux@gmail.com. It also updates .mailmap file to fix address for 'git shortlog' Signed-off-by: Viresh Kumar <viresh.linux@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>	2012-06-20 14:39:36 -07:00
Viresh Kumar	5335a639ec	SPEAr: clk: Add Auxiliary Synthesizer clock ... All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on values of eq, x and y. Fout from synthesizer can be given from two equations: Fout1 = (Fin * X/Y)/2 EQ1 Fout2 = Fin * X/Y EQ2 This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>	2012-05-12 21:19:26 +02:00