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3 Commits

Author SHA1 Message Date
David S. Miller
59abbd1e7c sparc64: Initial hw perf counter support. 
Only supports one simple counter and only UltraSPARC-IIIi chips.

Signed-off-by: David S. Miller <davem@davemloft.net>
 2009-09-10 06:28:20 -07:00
David S. Miller
a8f2226455 sparc64: Manage NMI watchdog enabling like x86. 
Use a per-cpu 'wd_enabled' boolean and a global atomic_t count
of watchdog NMI enabled cpus which is set to '-1' if something
is wrong with the watchdog and it can't be used.

Signed-off-by: David S. Miller <davem@davemloft.net>
 2009-09-08 23:16:06 -07:00
David S. Miller
e5553a6d04 sparc64: Implement NMI watchdog on capable cpus. 
Signed-off-by: David S. Miller <davem@davemloft.net>
 2009-01-30 00:03:53 -08:00