IF YOU WOULD LIKE TO GET AN ACCOUNT, please write an
email to Administrator. User accounts are meant only to access repo
and report issues and/or generate pull requests.
This is a purpose-specific Git hosting for
BaseALT
projects. Thank you for your understanding!
Только зарегистрированные пользователи имеют доступ к сервису!
Для получения аккаунта, обратитесь к администратору.
- Use new "wakeup-source" instead of "gpio-key,wakeup" in Z-Turn
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAlxiwoEACgkQykllyylKDCGAJQCbB4cK6W0fXAfw/Zi7mHBEo0yL
lxEAn3/zTTTB2DFB+kimxZFZcHJaEY11
=dMVs
-----END PGP SIGNATURE-----
Merge tag 'zynq-dt-for-v5.1' of https://github.com/Xilinx/linux-xlnx into arm/dt
ARM: dts: zynq: DT changes for v5.1
- Use new "wakeup-source" instead of "gpio-key,wakeup" in Z-Turn
* tag 'zynq-dt-for-v5.1' of https://github.com/Xilinx/linux-xlnx:
ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- New board support: Logic PD i.MX6QD EVM, ZII SSMB DTU, Phytec
phyBOARD i.MX6UL Segin, Y Soft IOTA Draco, Hydra and Ursa boards.
- Add regulator control for various sensors on imx6qdl-sabresd board.
- Add DISPLAY power domain support for i.MX6SX SoC.
- Add stmpe-adc device node for Toradex iMX6 module.
- Switch to SPDX identifier for imx6q-tbs2910 board.
- Add proper ksz9031 clock skew values for imx6qdl-phytec-pfla02 board.
- Mark I2C recovery GPIOs as open drain and correct and WEIM range
configuration for apalis/colibri boards.
- Small and random updates to various devices.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJcYo+8AAoJEFBXWFqHsHzO+D0H/3RYArKxp1FJ2QVS2w4uE2O7
eWycgtie8d4x84/hdMG72sU/x0hZm0v1kXUGO9Yt17dgX3Dg1Sfv7bECqZAHvG11
6dMuG5u3lCLjQQLieAAUvxpWFCne3gSWVQnb0o/zWiHBeGNQJt42hacLNYaJSqTL
Vao3wiiGTZvVih6B+ueFi4Im/VChEn5rnKmjCqkFTAlUIpVvzLZqY8Jy+vjVC3aP
5tLq8WnStJqgFgxtRpVKDsdu2KjJKCozpw0KZyM3MYQ4blGCCbFpFfyGfBeNves5
xCWrx//rt//ol09X5UXtz4T+/QKC5390styCA9m+XgSFcFSYKgjps+9iD+5a1tk=
=OH8n
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX device tree changes for 5.1:
- New board support: Logic PD i.MX6QD EVM, ZII SSMB DTU, Phytec
phyBOARD i.MX6UL Segin, Y Soft IOTA Draco, Hydra and Ursa boards.
- Add regulator control for various sensors on imx6qdl-sabresd board.
- Add DISPLAY power domain support for i.MX6SX SoC.
- Add stmpe-adc device node for Toradex iMX6 module.
- Switch to SPDX identifier for imx6q-tbs2910 board.
- Add proper ksz9031 clock skew values for imx6qdl-phytec-pfla02 board.
- Mark I2C recovery GPIOs as open drain and correct and WEIM range
configuration for apalis/colibri boards.
- Small and random updates to various devices.
* tag 'imx-dt-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (31 commits)
ARM: dts: imx: Add support for Logic PD i.MX6QD EVM
ARM: dts: imx6qdl-sabresd: remove reg_sensors' regulator-always-on
ARM: dts: imx6qdl-sabresd: add regulators control for mma8451 sensor
ARM: dts: imx6qdl-sabresd: add regulators control for mag3110 sensor
ARM: dts: imx6qdl-sabresd: add regulator control for isl29023 sensor
ARM: dts: vf610: Add ZII SSMB DTU board
ARM: dts: pfla02: add ksz9031 clock skew values
ARM: dts: imx6qdl-phytec-pfla02: add missing interrupt-controller property
ARM: dts: Add stmpe-adc DT node to Toradex iMX6 modules
ARM: dts: Add devicetree compatibles for LS1021A based boards
ARM: dts: colibri: use valid range configuration for weim
ARM: dts: imx6: Add support for Phytec phyBOARD i.MX6UL Segin
ARM: dts: imx6*-apalis/-colibri: mark I2C recovery GPIOs as open drain
ARM: dts: vf610-zii-ssmb-spu3: Pass "no-sdio"/"no-sd" properties
ARM: dts: imx: Add Y Soft IOTA Draco, Hydra and Ursa boards
ARM: dts: imx7ulp: add sim node
ARM: dts: imx6ull: change to use new compatible "fsl,imx6ull-usdhc" for usdhc
ARM: dts: imx6ull: Fix i.MX6ULL/ULZ ocotp compatible
ARM: dts: imx6sx: Add DISPLAY power domain support
ARM: dts: i.MX51: digi-connectcore-som: Add support for I2C bus recovery
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- more features for Endless EC100 board
- chip temperature sensor support
- fix ethernet pins
- add Mali-450 GPU
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAlxh4LQACgkQWTcYmtP7
xmWu3w//bOc1aqMh325KmhP+WXUJEp0Z+7/r8TcqYYW2UMdjqGKvYNREaL+cDKu3
6DOaWvTKrRHOJr1L4uSdg1NBEhH6Nzmb7r9bRLkj2xT5vT66pZIiMa4OETfvdvP2
TQ86MPUY69M6IJ2JzeYA34stItYanExDhosbaHmPSJqwvDdh0V932eBg4OY/IpEn
j4Hygf9HYSA5cSx7J2Ah1gUXzI66FcPlRBWrl+jeTS7qqU9GxYo8/8Hrgn6hyCTQ
dpQHvgsCdeHvsf8fRpulxH/aUo5u2nuX1/R8UrOWUmCPd2r3RBu0U27Ja7FJiAeb
s6OwLveAVeMS7Urrh3ylaFstbjg3CMtGvh1hnbWozF08yNzd6ihD5vsUED7vpxNr
hT8m8oC8hujP1CiIxFqbkPZsz/hWoagPOG2AtRNMehs+gVxOfD+CTkw3Y+x3+NrA
DwU9YzrKqFn4StSHJ6ccBE857gSH5QgOq0rLYiH1AlktHvXKh/hL/H82pFDJHZcW
OFZ2nAI9VCPDlx8tCbuH16BIqD03piT5ew0wWozG5uc/JP26stmMXHQlQVDxRju4
NsJiqGzAtgIK+jf2COVZJeYtOO9IYjPwrC0wJe2vWW7MTUBv0LSQDuBV2pTT/N87
pSqeusg80DuPC3WZLGU3whitwO6yg3NiWeGB6cweu3gWeQsMSig=
=PNC5
-----END PGP SIGNATURE-----
Merge tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt
ARM: dts: Amlogic updates for v5.1
- more features for Endless EC100 board
- chip temperature sensor support
- fix ethernet pins
- add Mali-450 GPU
* tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM: dts: meson8b: ec100: add the GPIO line names
ARM: dts: meson8b: ec100: improve the description of the regulators
ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt
ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature
ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature
ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature
ARM: dts: meson8b: add the temperature calibration data for the SAR ADC
ARM: dts: meson8: add the temperature calibration data for the SAR ADC
ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible
ARM: dts: meson: switch the clock controller to the HHI register area
ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins
ARM: dts: meson8b: add the Mali-450 MP2 GPU
ARM: dts: meson8: add the Mali-450 MP6 GPU
dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b compatible
ARM: dts: meson8b: add the APB bus
ARM: dts: meson8: add the APB bus
ARM: dts: meson6: add the APB2 bus
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Contains a single patch that adds the "jedec,spi-nor" compatible string
where appropriate.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlxdmP0THHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zoe4QD/4kFg14Rd4ERRZU31B5MNTmVETqEPx4
FGyR0FvMP0eNQCTJE/hrI9yiPVdB1ryE9YU//rsfIcezpTcsLbquEb2QqJqrP5y1
cdENJ7vi5kRV7xIh/UzkaYvg5qp2gYZVL7wMvPfuaSXqExcZqoyiNnHnGbP2oJzg
/GM1doEe8yck6WGLipJMyYtXkWAQydUwhNuWSAMXHKrgisIdB1/BSVXT3Ty9LpXC
doroWS/CeW3QN+VfqXPObXWM4f2EX7ApThblb7cvt55jbb8CenQXlszFGcPq4L29
ZV0s04mNBwXbJl4W0ilaXfCWceyjOx3EPeYJ/XA9khswyFVg7TVXV+AsevSbONya
bfm7c2x5Km35olPTlKo14qhcUw9ExfxyiC/rwi08/LI6wNZFSux9ZYNJL5EYPrxI
7F4ULcJaTG1K/LQy6xXrh98xRy0sSsSklFfGZ8DdOFuHEpHI+RQaWfOXYD4T+2QN
oZIA4x93zbRbvOQGkO7sMm1I9Oa3EI+PRG6QBHJyn/uMbaeA1gdtPr/gpwccTQo1
stgRLDwaxcUuvD0Byz2jAkgOoN2bPUdjqXWnKqHXFSiFoJj2IQOdJqNLw9NfB3j/
JrDOHHsJyHaAKovVAvaGi0zF83ZspVMyw4OnwyCCmeGqUX1BXwHCYzJWI7f+4WQS
R5wzq2pVU4+Opg==
=Cuag
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-5.1-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
ARM: tegra: Device tree changes for v5.1-rc1
Contains a single patch that adds the "jedec,spi-nor" compatible string
where appropriate.
* tag 'tegra-for-5.1-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: add "jedec,spi-nor" flash compatible binding
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* R-Car H2 (r8a7790) based Stout board
- Convert to new LVDS DT bindings
* R-Car H1 (r8a7779) and M1A (r8a7778) SoCs
- Describe HSCIF0/1 devices in DT
* RZ/G1M (r8a7743) SoC
- Correct sort order of the RWDT node
- Remove aliases: should be defined in board rather than SoC DT if needed
- Remove generic compatible string from iic3: it is not compatible
* RZ/G1N (r8a7744) SoC
- Describe LVDS and DU devices in DT
- Correct sort order of VSP and MSIOF noces
* RZ/G1C (r8a7747) based iWave SBC
- Enable RTC
* RZ/A2M (r7s9210) SoC and EVB
- Initial support
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlxdXz4ACgkQ189kaWo3
T75wbBAAqOyXvMCt7lGsov4i0e/lqSFl13uHv83Mk+PVvvT48H2g/ItitGDq4GYr
ItAYBRF66XcAKJbA30e4OvAk+yB0Y3iMT8KIR4Nca5ls9rn6NwbyBugZ65mizKEk
vIoA1sGpsWUrK0yxmGoIx9C6aX9qsh82ivdMpvwb1Kzy5oO59GCgJ9d/d+Q2KwvG
rycEPQwHLFIIijoNr0IH3ZiXhyfeEabGHg/EK/FVxJJNgQLjFW0ZogsZ/a49ptoZ
YZqEc2w13a+rWFTg7059UbzPNjJCq0/2lYRPthWTz9KzUyFgSZ+2GvawdoFSvBZ5
cf+6+qZkgkVvs00yajd6Q2t9IcyjeVmU+GBHFSO65wDRJknDN8sE1v/qHaAr0+Bm
My8Th55Tzak/d+6Zb6xP95kTiaUDpWQrjntMvg3AewiAcjDJasBSsU9EDBlEDh3W
VaQVkyyHtWwfiS0qFf4u0Rfgb2DIBYLvXzslipyZnsKih14+rC/S6N3j8rykrOoE
DTjh7Hi4k4xYwqwNFrg9lvGCoAG4aZddyat9SYfgTs65OmG7huyTH5vqtsmB3kN0
0a33nQ8xt24TH6wSHGB17GXeR9JEluqHC0Do9bbis1B6QiSBvcY+Ne1LtFN8O5sH
RNEcoqU1cCLVHvbRJL/3Y5bwYF22f0GvbMxO/vgdmcz2DSxbuL0=
=q0l0
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/dt
Renesas ARM Based SoC DT Updates for v5.1
* R-Car H2 (r8a7790) based Stout board
- Convert to new LVDS DT bindings
* R-Car H1 (r8a7779) and M1A (r8a7778) SoCs
- Describe HSCIF0/1 devices in DT
* RZ/G1M (r8a7743) SoC
- Correct sort order of the RWDT node
- Remove aliases: should be defined in board rather than SoC DT if needed
- Remove generic compatible string from iic3: it is not compatible
* RZ/G1N (r8a7744) SoC
- Describe LVDS and DU devices in DT
- Correct sort order of VSP and MSIOF noces
* RZ/G1C (r8a7747) based iWave SBC
- Enable RTC
* RZ/A2M (r7s9210) SoC and EVB
- Initial support
* tag 'renesas-arm-dt-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: dts: r8a7744: Add LVDS support
ARM: dts: r8a7744: Add DU support
ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB
ARM: dts: r7s9210: Initial SoC device tree
ARM: dts: r8a7779: Add HSCIF0/1 device nodes
ARM: dts: r8a7778: Add HSCIF0/1 support
ARM: dts: r8a7743: Fix sorting of rwdt node
ARM: dts: r8a7743: Remove aliases from SoC dtsi
ARM: dts: r8a7743: Remove generic compatible string from iic3
ARM: dts: r8a7744: Fix sorting of vsp and msiof nodes
ARM: dts: iwg23s-sbc: Enable RTC
ARM: dts: stout: Convert to new LVDS DT bindings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Our usual round of DT changes shared between arm and arm64.
We have a bunch of changes for board, improving the eMMC support on the H5
variant of the All-H3-CC, enabling HDMI and reworking the CSI driver.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXF1X8QAKCRDj7w1vZxhR
xX9ZAP9KwFKKehrS1QJjTHKeowUKEnRHuDj2MlwTZJgCw/AMMgEAzgRZwY/VH/Os
aQIhJho9hWmBE0dePIZuWzzCp1giNw8=
=7jQV
-----END PGP SIGNATURE-----
Merge tag 'sunxi-h3-h5-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner H3 and H5 changes for 5.1
Our usual round of DT changes shared between arm and arm64.
We have a bunch of changes for board, improving the eMMC support on the H5
variant of the All-H3-CC, enabling HDMI and reworking the CSI driver.
* tag 'sunxi-h3-h5-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: h5: libretech-all-h3-cc: Mark eMMC HS-DDR 3.3V capable
ARM: dts: sunxi: h3/h5: Drop A31 fallback compatible for CSI controller
ARM: dts: sun8i-h3: nanopi-m1-plus: enable HDMI
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add SMMU node for Stratix10
- Add vendor prefix fo Novtech
- Add a new 96Boards Chameleon96 board that uses a Cyclone5 SoCFPGA
- Add missing reset properties for all IP on Cyclone5 and Arria10
-----BEGIN PGP SIGNATURE-----
iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAlxYYAAUHGRpbmd1eWVu
QGtlcm5lbC5vcmcACgkQGZQEC4GjKPSfPA//a013n1vCV9Wz6RsbXNRODXzhV6FN
9uPWAdbkuWrCvDFAH+9s/0nMwxAj8f1HCEK9J07CPRcjcLPO7iHfIUeJ4lbCNCXZ
1ZuLDdK0Y4GjziJ4xlUP0JvUpJXtRKo+XDXVC+jNAMQy6wQpsEYdEwpeTPo94jrv
X0Zait3PeaY6ai6ImzV4QOYYmZ9GhRHjNY/Hc8jSsZeMWk+sMWygExlUngXlpO8c
dvK1Z4dfhrRZyJ/ewjjb/D0eekq8XiIfGmI4A2Cox3A73XAmtPEL3MT57BbPnq7f
jmNmlh7yRrxZHVErSt0dJTOJ6dNx+McuuwSmDL1vR19M44JUbVOjLjDUEwA7tSmr
eQXVhGuYHfxgJT0CeEBIHJAxPZfTqy68IijZYXv4aWimFdsbeAtraY7PKeZ/TnOP
3Aa9GDSks5NsAGVR5AltiNRmZujyQktbcNU8TcNt8tc19Kub8Q9GVhsmPUIKEov8
oAeXq4xbvGe6Ike6cfR1H+P14mgpbxJSZwGQoqky1T3lWqFBhl/93/ixpzt5jMWX
96tHA7VuZ7+in3BoqzHNxZ2PWpHScd3UScLxzxFEotW2nCofXCLCVkW+Zl8xWLa9
eu5GXE0ZzA04Elaagj2MM/rTsIgWFWqROq4A3Za6k5AB7quThr1yMoL+5Q5keOlO
4xAhCKudZb74BS4=
=8OgV
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_for_v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA DTS updates for v5.1
- Add SMMU node for Stratix10
- Add vendor prefix fo Novtech
- Add a new 96Boards Chameleon96 board that uses a Cyclone5 SoCFPGA
- Add missing reset properties for all IP on Cyclone5 and Arria10
* tag 'socfpga_dts_for_v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: update more missing reset properties
ARM: dts: socfpga: update missing reset property peripherals
ARM: dts: Add support for 96Boards Chameleon96 board
dt-bindings: vendor-prefixes: Add Novtech Vendor Prefix
arm64: dts: stratix10: Add Stratix10 SMMU support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Fixup GIC IRQ flags and GSBI state on MSM8660
* Add USB OTG, gpio ranges, and Wifi support on MSM8974 Hammerhead
* Remove skeleton.dtsi on IPQ4019
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJcV5CEAAoJEFKiBbHx2RXVXysQAK08L4mNPGVLt+NkHVr9kLcD
CUq5emEizYWs1wdA4H+2Zzf/EEMAoGHLI0uX3WnP55fPTbLhVBVVIlvv5+J9KF9T
Y37LF4mMho7JvmDUfq9t4brx9sosduEVpbLyQcmR+avWWbSVjmgajPCyBTOgR/0C
2wUnl0mKDSsZO8fqNiQd8AkeXfkBSDFCYOq6jn2MZ6Aop93Lg7GqZ4/hWp/WRA8Z
9AhgGLNF02O4mIyfZI8k9tf8CYjHNlm3ceIDj1uRBfMtyhLQZDoAWc+zVXQ2njbW
5lLMPdbqZzepNU9ou/4Z4DeVKwAt0EnaOcDiMi7JJ3o8rtQXI9UL0QnKJK1Rcj7K
82XKP+lbzB2/JI62PSk7kT+bQ1EmmJn19wRcjBtP4L+gCdH0kq2QopVEVkhUU7pg
y5cwHKLtKtYlXeXO27h0amYY+xy/MgMfgJMAhxsn2hj+U3N7DJKYSh5nfWpVU2BP
ztobWTvCvnxPTGFXI9Txl00KVgy5Og2pWaMzkge3yAbesqsPNjJamk+BGn8qL75X
ViBnHMmvH2RBgROLcHgJcjrkdeu5xNwps38xlb/5K9L4jT8wPAcal00y/qMv1saR
A56zL+wtuHEOCqyULvKAzNzduVdEoQechCYueZTm+5M/pXkrkddIDcs6xUGvxtPX
bw9AhstcXIl49QRKgeUg
=0M2a
-----END PGP SIGNATURE-----
Merge tag 'qcom-dts-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt
Qualcomm Device Tree Changes for v5.1
* Fixup GIC IRQ flags and GSBI state on MSM8660
* Add USB OTG, gpio ranges, and Wifi support on MSM8974 Hammerhead
* Remove skeleton.dtsi on IPQ4019
* tag 'qcom-dts-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
ARM: dts: ipq4019: Remove skeleton.dtsi
ARM: dts: qcom: msm8974-hammerhead: add USB OTG support
ARM: dts: qcom: msm8974: add gpio-ranges
ARM: dts: qcom: msm8974-hammerhead: add WiFi support
ARM: dts: msm8660: Fix up GIC IRQ flags
ARM: dts: msm8660: Mark two GSBI blocks "disabled"
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Here are the changes for ARM NXP LPC32xx and ARM NXP LPC18xx/LPC43xx
devicetree files:
* added dts file for MYIR Tech MYD-LPC4357 development board,
* two missing properties are added to LPC32xx keypad controller device
tree node, this fixes a long-standing problem with its initialization,
* LPC32xx PL11x LCD controller device node got corrected properties,
which allows to use it with a new PL11x DRM driver,
* output voltage level on one of Phytec phyCORE-LPC3250 fixed regulators
is corrected, the fix is needed to remove duplicating platform data,
* Phytec phyCORE-LPC3250 board gets a description of a kit LCD panel,
this completes setup of CLCD device tree node for the board,
* added unit addresses to memory device nodes on EA and Phytec boards,
* fixes of ordinary warnings in dts formatting like leading zeroes,
unused address and size cell properties and so on.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEETKMJMWSwX7CFTVIOqj3i2jwlOWUFAlxXTzIACgkQqj3i2jwl
OWXBRA//RCAfC/GhIyZF1uHIhj/G85sAWuGSYQ90+fEVtyzb1Y+yeBRKkNH2Xi8C
LkSzD58z/1BTaYz68EaRENU3xCkBcBHH8ZymqJP8/pG+/AoLVIg7/wkeFj/BCC80
rESTV4IjTFdbAaqmM8Y/rcWuPTs5fgxZzFdCgqY0FuTee5hx5aLQkA39cIPWJLJz
Ox+e/Yhs00blWZUFyitP5sd/rnVeuNXWqY0VnN8hG4oH4+GJOA8QAIzzq1DTKaj0
43073ymRw4ZOry0qfsbRvjQZwvSAQD+kZx24DXwP+6YFdW8DqdAZPkuCYYMV10JO
tiOg6hHHjM1lKJWom/6N1Z9layMZeyPxBRYQ2Tpn3+5Or05iHgAhbYv5kRvIBZ8W
cL8hA9SNb/g4yRa67GBINdGHlf3nRBvqDgOR0OQEF3Q/JTFferJOb3MhGuIX1fS7
39JRIndLJD10SoK/Nezvc68myei8aQ+YTQBzaNkm3q4q4SuLF9nEb92s313yvzKv
vBwMuaGuTL+pBvDR3qGsFHxrExj1DIbecYqGdvGj0lmSZbNPWeR2ZSj6XGfT18x3
pCmr7C6brY6jWsp6p8nG7ovFkPqv3X3x/gBszLFGFaEedkssabfLesWdZooHIAgJ
Fa6Lc2M7AAwxHT1YDn6+ojrr/yhaQoaray/+aOT9WAwAhElpc24=
=J1uJ
-----END PGP SIGNATURE-----
Merge tag 'lpc32xx-dt-for-5.1' of https://github.com/vzapolskiy/linux-lpc32xx into arm/dt
ARM: lpc32xx: devicetree updates for v5.1
Here are the changes for ARM NXP LPC32xx and ARM NXP LPC18xx/LPC43xx
devicetree files:
* added dts file for MYIR Tech MYD-LPC4357 development board,
* two missing properties are added to LPC32xx keypad controller device
tree node, this fixes a long-standing problem with its initialization,
* LPC32xx PL11x LCD controller device node got corrected properties,
which allows to use it with a new PL11x DRM driver,
* output voltage level on one of Phytec phyCORE-LPC3250 fixed regulators
is corrected, the fix is needed to remove duplicating platform data,
* Phytec phyCORE-LPC3250 board gets a description of a kit LCD panel,
this completes setup of CLCD device tree node for the board,
* added unit addresses to memory device nodes on EA and Phytec boards,
* fixes of ordinary warnings in dts formatting like leading zeroes,
unused address and size cell properties and so on.
* tag 'lpc32xx-dt-for-5.1' of https://github.com/vzapolskiy/linux-lpc32xx:
ARM: dts: lpc32xx: ea3250: beautify gpio keys children nodes
ARM: dts: lpc32xx: ea3250: add unit address to memory device node
ARM: dts: lpc32xx: phy3250: add unit address to memory device node
ARM: dts: lpc32xx: phy3250: setup LCD controller to panel interface
ARM: dts: lpc32xx: phy3250: remove regulators umbrella device node
ARM: dts: lpc32xx: phy3250: fix SD card regulator voltage
ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller clocks property
ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller variant
ARM: dts: lpc32xx: reparent keypad controller to SIC1
ARM: dts: lpc32xx: add required clocks property to keypad device node
ARM: dts: Add DT for MYIR Tech MYD-LPC4357 Development Board
ARM: dts: lpc32xx: Remove leading 0x and 0s from bindings notation
ARM: dts: lpc435x: remove address and size cells from gpio-keys-polled nodes
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
for 5.1, please pull the following:
- Dan relicenses the Luxul DTS files to GPL 2.0+/MIT
- Hao adds support for the Phicomm K3 which is a BCM4709 SoC with dual
BCM4366 radio
- Stefan adds support for the Raspberry Pi A+: binding and DTS files. He
also provides a bunch of DTC warning fixes for the different RPi DTS(i)
files and adds support for missing GPIO lines on RPi 2/3
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAlxVz5oACgkQh9CWnEQH
BwSx3w/8Dtph3vW+OjerHao0vEXM85iYGUyydTvmOB+lM3Cq09vtqgXNX8xTnH8F
jFv5o//vdrLF1JFFthJeR06MGr8BOEncQJKKCEXnEGdkaL50CzvH5pD/q1iOm5ig
qrXiBy8hNd/gmkmj/BUUjKQLViUzelameGOezAI5RE+QzkraO3rIPFItT1R+X5uQ
pc6CPpEmRXWvcUn3QOimqaFW+mePqoez1xA12bBCw9DXAUKX/p3sglTC+kA7t0zC
DfgXYpGhvIk0e7inJIk+rLMJKbD2Pmvd3hS0XT6AnObRFApYwMiso3BVTvEbFvv8
ebt9j+QZmJFcVp68NDErrNjq4yjq+yUqhikd/G3KGfPzCWZHIC4LFQu3LEZjq61Q
NTRxNgRvUwdifRWEAGYWZJdjJSWtnrDdoR3h446bv5WELGF2WDHv5kRs+NEkxkwK
fTHPRFMLAuai6nFiIEnSHfBbcZEH7R0R8+FKmoPYFz6KbU54EzJYDhv+DTjG713K
xqdfNTwyZhC3E9fxXZGGV1Jc/u/HlCuCRiGXIaUAoOz6PTZ6mR/rd8KhlwrzHFfS
Gazr/mOviYAiHzjdFGij3GOL2rgO/izMOEorPtH2bJj01VmmAsJygbZn9oSoSAEn
VxIAiAnT2ShiVuXUVxAvKGtKhu3x3Da1VychBYVw30jzkkgzvHU=
=Ykbm
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.1/devicetree' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM-based SoCs Device Tree updates
for 5.1, please pull the following:
- Dan relicenses the Luxul DTS files to GPL 2.0+/MIT
- Hao adds support for the Phicomm K3 which is a BCM4709 SoC with dual
BCM4366 radio
- Stefan adds support for the Raspberry Pi A+: binding and DTS files. He
also provides a bunch of DTC warning fixes for the different RPi DTS(i)
files and adds support for missing GPIO lines on RPi 2/3
* tag 'arm-soc/for-5.1/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm2835-rpi-zero-w: Drop unnecessary pinctrl
ARM: dts: bcm283x: Add missing GPIO line names
ARM: dts: bcm2837-rpi-3-b-plus: Clarify label for STATUS_LED
ARM: dts: bcm2837-rpi-3-b: Use consistent label for HDMI hotplug
ARM: dts: bcm2835: Fix labels for GPIO 0,1
ARM: dts: bcm2835-rpi: Drop unnecessary #address-cells/#size-cells
ARM: dts: bcm283x: Fix DTC warning for memory node
ARM: dts: add Raspberry Pi 3 A+
dt-bindings: bcm: Add Raspberry Pi 3 A+
ARM: dts: BCM5301X: Add basic DT for Phicomm K3
ARM: dts: BCM53573: Relicense Luxul files to the GPL 2.0+ / MIT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1. Extend support for Aries family of mobile devices (e.g. Samsung
Galaxy S) based on S5Pv210 SoC: DRM Rotator, FIMD, PWM vibrator,
power off, touchscreen, Broadcom BCM4329 Bluetooth and cpufreq.
2. Remove hardcoded bootargs on Galaxy S family (proper support in
U-Boot).
3. Fix minor DTC warnings.
4. Fix Exynos4412 Odroid X2/U3 conflicting eMMC GPIO settings and regulator
properties.
5. Fix the eMMC RTSN pin breaking proper reboot on X2.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAlxUmBoQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD115MD/wLf75FsakZ21mCRPmQ2DNhRzlZezCi75YH
7a/AO9j9I2+gL5Bg9oIHS/5l3YnZSDqYfBj61fzHIEp5lzD1UwVBJLUsDS00NKHt
B58/dH2V9pFj9ZyUDJj7MdMCrt7dNznGDOeztG8XRWd7AeoENP3ysDnjvd6FmGLY
2AgoTrql0cGzTwIcL7dTgg1dEdwSTPyQ1rXovAnF6ylRwFnts9xWRgdIm2/IAzHz
/vgdXzApFykWaoEH+5NIskNQZuGgDKi5zAT4h1yMcOamG7FxBRGzaWJiG+YhQC/M
c6wMaOZxnTRDOhLpcVsNS3i1FCIN6TtbAq0kMDz99v7o2RJm3AdroM+Hm4bXc4sU
JKk8PVufQxk37JIygUCBESwVVNhnX4ZzIGQSxX74k9rvLEYjdnzEU0o5s/69h/q+
1kK8t0/2CPVXKRKkNV7X0wAyLYoNtNh84v45Xyp0EJLHgMA2E2L2zojFqKISlilG
4ctnWG9se7PCGBVLAHAX1z2htMPQ0rHdSYi7U5Z5rJoRdVy96CcYMPXCtKxTtqea
02tNyXxi+bgizsQBSTpwG2+66p5vAIwA/PYLM4b6ZcTILmS0jjCZCUS6wfxYYa22
5Y37sPNSxjAOireg0QQJiBiiiHn+0qYakdw/t11zJ8tc2JDhDVD5tYaahpS8IH5g
NDHCIjBDZQ==
=9+iJ
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM changes for v5.1
1. Extend support for Aries family of mobile devices (e.g. Samsung
Galaxy S) based on S5Pv210 SoC: DRM Rotator, FIMD, PWM vibrator,
power off, touchscreen, Broadcom BCM4329 Bluetooth and cpufreq.
2. Remove hardcoded bootargs on Galaxy S family (proper support in
U-Boot).
3. Fix minor DTC warnings.
4. Fix Exynos4412 Odroid X2/U3 conflicting eMMC GPIO settings and regulator
properties.
5. Fix the eMMC RTSN pin breaking proper reboot on X2.
* tag 'samsung-dt-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Fix pinctrl definition for eMMC RTSN line on Odroid X2/U3
ARM: dts: exynos: Fix eMMC regulator properties on Odroid U3 boards
ARM: dts: exynos: Fix conflicting fixed-regulator GPIO flags and properties
ARM: dts: s3c2416: Fix xti node's missing reg property warning
ARM: dts: s5pv210: Fix onenand's unit address format warning
ARM: dts: s5pv210: Add DMC nodes
ARM: dts: s5pv210: Add support for more devices present on Aries
ARM: dts: s5pv210: Add reserved memory for MFC on Aries
ARM: dts: s5pv210: Remove hardcoded bootargs on Galaxy S and Fascinate 4G
ARM: dts: s5pv210: Use correct fimd variant
ARM: dts: s5pv210: Add node for exynos-rotator
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
improvements for rv1108 as well. RK3066 got support for the core
display components and the Edison tablet got its touchscreen added.
Apart from that a wider fix to drop display-wp usage from places where
it shouldn't be used, a pin fix for Edison and a cleanup to prevent
rk3036 board from defining sound-dai-cells for core components in
each board separately.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlxTAPIQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgYbQCACiWIYVLrOwOPSgDo3xRFygo2Bmlo2EncEz
UZM0z3gQpzQ8go7Ms6eqL7qRoMI14Cc3XT6dNkzjRBIBaJAi3LXy1G4CLMzxuurD
qri6shmJv94TfBNISJ9FOQYqJRxSK1z4ncp6iXNeOgOa9NCkqSXkHTOve8oVAxfj
nBnMAA0kkX/haF4pNaLoDUv3ppMi7UHjAuoyJMNaTFqVG9qjR1DPNBnCGdYZGacU
Xkb/9n/QOLsJc/yoMcUno+Q5tUVkLsxQVhsApf9Tf7Hd76WV0dgIzi0hENvoKJjK
TwfHz26NyNzw9KbX5YJmNGUAbgesjVBx5AXJk+pBZvrBWGUDtixE
=VDwG
-----END PGP SIGNATURE-----
Merge tag 'v5.1-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New board the Elgin-R1 based on the rv1108 soc and a number of small
improvements for rv1108 as well. RK3066 got support for the core
display components and the Edison tablet got its touchscreen added.
Apart from that a wider fix to drop display-wp usage from places where
it shouldn't be used, a pin fix for Edison and a cleanup to prevent
rk3036 board from defining sound-dai-cells for core components in
each board separately.
* tag 'v5.1-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: clean up the abuse of disable-wp
ARM: dts: rv1108: Add support for rv1108-elgin-r1 board
dt-bindings: Add vendor prefix for elgin
ARM: dts: rockchip: rv1108: Add spim0 and spim1 pinctrl groups
ARM: dts: rockchip: Add missing dma-names SPI support for rv1108
ARM: dts: rockchip: add rk3066 vop display nodes
ARM: dts: rockchip: add focaltech touchscreen to rk3188-bqedison2qc
ARM: dts: rockchip: fix cif1_pdn pin on rk3188-bqedison2qc
ARM: dts: rockchip: add HCLK_HDMI to rk3066 vio power-domain
ARM: dts: rockchip: move rk3036 i2s sound-dail-cells into soc dtsi
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
mic input on da850 LCDK board.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJcVAHxAAoJEGFBu2jqvgRNKDsQAIQxTufIRkRxbd+diYCcMlas
9HINvZklP/Utqg4oo5tEaAH8An1E7AR67UcOwvCzFU4tN6vBMsnZN+oaBJ9Tsfbi
0fB5lld/WYAN/+4wQpv6lOI1A2kNohi9nKZLiwDvEhFFTevoeciS8Ypepl9h7Zr4
PyQ7xthz29vsbE8TzpFIs4225VrqFCjXMa5hzrDmuaj4Fn6wMBwhgnLbfW8plg2j
FzxZj1t5ZoOUIOkokdGXwcPMkY86cVc0ntEQLWy8lRqnX3zzpYbJ4zk7Fg4XH2wE
DzJSXeJIPO8nqN3XXmDYEXSmO0X3KRHam5ggVKtaQVPEur04AsJTaJqhUlQGKDi+
LmGXi0d/SGg581VPbsgF6rk9Suxzq6EPHZ6zkx1AFLnHfXzTSFOoUdgkQ7pqarM/
529dYiVrWztk3NB0mYCI3q30l7SIuKh9R8WlAXhAnHCb8v2467VKBvIXcPI3UrSz
OESTln6gl9ZKkkp6ZlGFfIWWTzdoSg2blO3izIjVVzvPDFF7J4Sa2/fHORGAJBlt
slFUEjc5PicXj60rG+1jRunGu0YLUjqvJFSJzH8nGnUsBbHhnFhf0/eYzC+Li+2R
pUk6U+7UP9rSdqUYYTw+U+wHzWGYcDxcBMjUg+qt6djFm2uGGyLAHujDyXnFyP5z
42t2Zt3tnsjJh22J/uTH
=6oqi
-----END PGP SIGNATURE-----
Merge tag 'davinci-for-v5.1/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into arm/dt
DaVinci device-tree updates for v5.1 contains a patch to enable analog
mic input on da850 LCDK board.
* tag 'davinci-for-v5.1/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: dts: da850-lcdk: Enable the analog mic input
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This series contains board specific dts updates and few minor
clean-up changes:
- add stdout-path for am335x-chiliboard
- add wlcore wakeirq for omap3-evm, pandaboard and omap4-droid4
- remove unnecessary address-cells and io-cells for am33xx
- replace deprecated linux,wakeup with wakeup-source property
- use spdx license for am335x-shc
- configure ethernet pins for omap4-sdp
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxTIEkRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXM2BA//cCf3AQJ3NsQu0Ptg8gA9KE7QgJGNS2Om
kyBr8lI5VKOS7BTNTvocplOTIzaAPLGivmQVlmcOl5AIk4CcfCjzo0Z67Z/9QM4Z
JMmcrhLR+R5Ha6xpWMq0C9fYnV4gbPmZExr+MIg8vOx65ln6j4yYATFNX+2pc7SN
BAXmj5AHr06CTKS6gjPYJ4Mb/YNNcf2WB2fgSmXff8TQ5zO75GnJU/RY80kdQyB4
aHD4KKg9exuRRJxf/mDnQMos6hkanUlciZ0I+QgIizL3/+z8T0psRjNIet5zoi/n
8yqlXT60T+C8t3s9KoVt7Ls2sdW5tZUz28V6Us7sYuEPi2BKXhaU5tm1mjrdRfTx
Iny+d/otKgGMjiuX040GUezzJMdZUz5N5Ah/WaGCgCpyvGMuIosqprGxnBBOH+pp
2sN8Quaq80x6kKkVFwrU1fsU4QsBlc2vqEXMb/DSZRnT+aQn8Eek6DB++nl/bHuy
RxlXR5xg/nFGN4XeFIlIEJjSEBYb6V+6erln4XkPPhbSE9v/Dj6ycFIF5W0B/lDB
gtOHhTH0kn154A3Wtx6BB6sntjRQ+mr8LX2CcfR18VPg3Jh4L0rjpxJ4niIt5VG5
dPIkZPIPHE3fqJTLSpD1yFydIg3xsLv5MZ1i5Tz2B4cOMgwwNoR/kUN9xZATThA4
NE+4kOVt3rU=
=6JIq
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.1/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
dts updates for omap variants for v5.1 merge window
This series contains board specific dts updates and few minor
clean-up changes:
- add stdout-path for am335x-chiliboard
- add wlcore wakeirq for omap3-evm, pandaboard and omap4-droid4
- remove unnecessary address-cells and io-cells for am33xx
- replace deprecated linux,wakeup with wakeup-source property
- use spdx license for am335x-shc
- configure ethernet pins for omap4-sdp
* tag 'omap-for-v5.1/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap4-sdp: Make ethernet working even if booted with latest u-boot
ARM: dts: am335x-shc.dts: Switch to SPDX identifier
ARM: dts: am437x: replace linux,wakeup with wakeup-source property
ARM: dts: am33xx: Remove unnecessary properties
ARM: dts: omap4-droid4: Configure wlcore wakeirq
ARM: dts: Configure wlcore wakeirq for pandaboard
ARM: dts: Add wlcore wakeirq for omap3-evm
ARM: dts: am335x-chiliboard: Add stdout-path property
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Two changes to add support for McGill University's IceBoard telescope
ARM + FPGA instrumentation board. This board is used for several
telescopes around the world, see the related device tree commit for
some interesting links for more information.
Note that these changes are based on the related ti81xx soc changes.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxTHpMRHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXPIjg/9F44dfPdlGf8Dk14pTEGpOUOBIbNoSpod
4IKB1DDu84NEVeoH8cDxp98U++Bra/JGwUwa5gEkZOa/qZG/iTpcJckpLCeKu3qf
2OKb+cU1+ByYUJqn2Ji8LyQ6Spi2XafGKDCGFcXB7XcDx1SgMlOllQLaf2lPVtsq
IUsBHzmtFbj0DZ+laEGQTQxnSefEFvLpb5r7lM7grA3AuNQFSxz3QAy2QE7Cbfxs
IeVbVeDBqI6OtbYwW7muOds19CZToqIVe3kNydxEXvUdBB3qzB8rIy1a6kbH4lgH
0+J4TqjZ7Iwqlcew9h4CO1AO3P11/PKdFM4lQt8hA9e90qM48zW1WEeMbteliP6x
XnEo5sQQd62Qf8lQUeh8b7uw/6fABQIML7kdqcIiAKC6BfWClJv1wLLpRPV9UGGm
CKDkTsMEuEZPBM0TVf1BZVzQA6pwVO0FJfmjcG/yvUDATGNBj0zCdUKpiBVVnXa+
kTSQpLlbkuDARg/KVTVEkNf9CsqzNJyah5BhYbZUPhyoxs00vRJRRa+4Ay0Gpw7O
HggCvLL73y+8QNMOUj9FKmHA+cnIqB15tRmQ3+K3FCBpmmOediS6hp1Kufk9e9Y/
cTONQQUR2IqwnTdYoxR093xEdPkksQO7FOm/KmSLU/PgaqZNmAje6kZf9OT/tv53
Fn/96rJvrBE=
=ucZD
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.1/dt-ti-81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
dts updates for ti81xx for v5.1 merge window
Two changes to add support for McGill University's IceBoard telescope
ARM + FPGA instrumentation board. This board is used for several
telescopes around the world, see the related device tree commit for
some interesting links for more information.
Note that these changes are based on the related ti81xx soc changes.
* tag 'omap-for-v5.1/dt-ti-81xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: Adds device tree file for McGill's IceBoard, based on TI AM3874
ARM: dts: ti81xx: Add dts boilerplate for all GPIO and SPI peripherals
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlxS/KYQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgUdCB/9d8IN+iZUxo1TX5QS0ov+1FYhkly6FNEj2
JGQYL5zCDGe5RvgfyqL3vi3kHFQoDIHjsRQBUl14/ryo+InIl8ZJWl38tFjHYmdw
o883g3zyJLbwKrsE2RBtWtWsoK5TSwbV7xR3JO8tHWFV+mXDUUcFFXpR5VRjnQ9l
XsjvvzznfQQLpUzJy5OAjTAhtvkXExM74h4MpwIXtyeqrWUI73a6uBUeY6Js43rZ
zTfyv8Ikla3eP+fMQqf60CwKjxhQwyG7/7UxWp7iIatsUMeC5VLRCZuM7l109pH0
hKQLWybzcReCPfTqQ2rAwAhBQmQIpEvdwhFk5WA1mmqMi/d/Zdoh
=oEEi
-----END PGP SIGNATURE-----
Merge tag 'v5.0-rockchip-dts32fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
Drop one non-existent component from powerdomain list.
* tag 'v5.0-rockchip-dts32fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: remove qos_cif1 from rk3188 power-domain
This series contains two SoC regression fixes and one uninitialized
variable fix:
- Fix inverted nirq pin handling for omap5 that started producing
warnings with earlier GIC direction checks and took a while to
understand and confirm. Basically there are two sys_nirq pins
that are bypassing peripheral modules and inverted automatically
by the SoC and need to be handled with a custom irq_set_type()
- Recent ti-sysc changes caused a regression to the pwm-omap-dmtimer
code where the device tree handling code for timer source clock
gets confused. It looks like we can remove that code eventually,
but for now we just drop a bogus pm_runtime_irq_safe() for the
timers with the related quirks caused by pm_runtime_irq_safe(),
and have the standard assigned-clocks and assigned-clock-parents
deal with setting the source clock
- Fix potentially uninitialized value for display init code if
regmap_read() fails
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAlxR8TERHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXNhNQ/+JfJVPT4SyF0KQz8BJYYF2bVvJyFv0kBR
XrGIi6KTdoiN9Bm3Trt1rM+YJpS2Ii2YAc2frGVE4qMHw6ZUZA1uDxDl6J6C04H+
Eb7XrYnt0hqzuLfmx5ubX2eem92AgszWou85v8flwIk7dUJWtNkhUFTZtoDujLSM
ZnBWcG+9MuSWGpcigu1O9Qt/ePwQerxAksE46fKlbjZrk03j/Eh3A3YCTInV7sgR
Dl+jZhfva92GupcBzMsjWYaqLzdBG7Cq4pGfbhyTHdaapt26nK/osuNPh+zFgWZe
ppKbyPcQQ9ph9qJWd6A/BN9uN3zQfBwwtjVWaGX0LqahsEcIQyjj6QSKMjbYdNOK
fdXuL3Du6zMeQlez1mjS9xBU9s8B1N60F+vCVanDZW8ynkPZp7gBnG5vxC9ZEfR3
ZVLzhWMwejmidnPi9Clm/OHiU7ExAKwS6ql7qnhZS/3l8sdzm6Rs9ZQ1UO7scdfc
8MrB6wKNYQHPeoDLxmOa+DvSn64BPEboZtm2IoP+fvOvoJoffcM7FSxWTkkElrLO
6jgtRRm6Raw4vJvWmSJVIH8lpzthnOmdhtf+Ni9ZKysAPmj2N2uROdcjlqgOBvCf
xagW4iSUXMLNa2W1IgcTOxeAQs+ASVm3AvG02kx1ImMlnWrLJQO2yOW7DYdd6sCJ
x23XUpsiFeA=
=5oVS
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v5.0/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
SoC fixes for omaps for v5.0-rc cycle
This series contains two SoC regression fixes and one uninitialized
variable fix:
- Fix inverted nirq pin handling for omap5 that started producing
warnings with earlier GIC direction checks and took a while to
understand and confirm. Basically there are two sys_nirq pins
that are bypassing peripheral modules and inverted automatically
by the SoC and need to be handled with a custom irq_set_type()
- Recent ti-sysc changes caused a regression to the pwm-omap-dmtimer
code where the device tree handling code for timer source clock
gets confused. It looks like we can remove that code eventually,
but for now we just drop a bogus pm_runtime_irq_safe() for the
timers with the related quirks caused by pm_runtime_irq_safe(),
and have the standard assigned-clocks and assigned-clock-parents
deal with setting the source clock
- Fix potentially uninitialized value for display init code if
regmap_read() fails
* tag 'omap-for-v5.0/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Variable "reg" in function omap4_dsi_mux_pads() could be uninitialized
ARM: dts: Configure clock parent for pwm vibra
bus: ti-sysc: Fix timer handling with drop pm_runtime_irq_safe()
ARM: OMAP5+: Fix inverted nirq pin interrupts with irq_set_type
clocksource: timer-ti-dm: Fix pwm dmtimer usage of fck reparenting
Before we fixed up the interrupt hierarchy for the SSBI
GPIO controller, we had to use the PM8058 directly to pick
interrupts. After making the interrupt controller work properly,
we can reference the real interrupt parent.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add interrupt controller properties now that ssbi-gpio is a proper
hierarchical IRQ chip. The interrupts property is no longer needed so
remove it.
Note that the IRQs started at 24 instead of 192 like all of the other
PMICs. This is the same IRQs as the MPP for this board. qcom-pm8xxx.c
doesn't set the shared IRQs so this is highly likely to be a copy and
paste error.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add interrupt controller properties now that ssbi-gpio is a proper
hierarchical IRQ chip. The interrupts property is no longer needed so
remove it.
This change was tested on an APQ8060 DragonBoard.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add interrupt controller properties now that ssbi-gpio is a proper
hierarchical IRQ chip. The interrupts property is no longer needed so
remove it.
This change was not tested on any hardware but the same change was
tested on an APQ8060 DragonBoard with no issues.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the PHY as a new node. The PCI-e controller node gains a
phandle property that points to it.
There isn't yet any code in the kernel that uses this device's
registers, but it will be added for a PCIe PLL erratum workaround.
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
The lcd display of the gta04 has a backlight but the backlight
was not referenced in the lcd node, so screen blanking did
not turn off the backlight. Fix that.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Bosch Guardian is a TI am335x based device.
It's hardware specifications are as follows:
* 256 MB DDR3 memory
* 512 MB NAND Flash
* USB OTG
* RS232
* MicroSD external storage
* LCD Display interface
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
[tony@atomide.com: updated to use #include]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Most of the legacy "gpio-key,wakeup" boolean property is already
replaced with "wakeup-source". However few occurrences of old property
has popped up again, probably from the remnants in downstream trees.
Replace the legacy properties with the unified "wakeup-source"
property introduced in the commit 700a38b27eef ("Input: gpio_keys -
switch to using generic device properties")
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The EVM consists of a system on module (SOM) and baseboard, and LCD.
This patch adds a DTSI file for the SOM and baseboard separately,
then a wrapper to combine them and specify processor type and a
LCD information.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Now that all sensors supplied by reg_sensors have supported
regulator control, reg_sensors does NOT need to be always ON,
remove "regulator-always-on" to save power.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The mma8451 sensor driver has supported regulators control,
assign the power supplies for mma8451 to enable the control.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The mag3110 sensor driver has supported regulators control,
assign the power supplies for mag3110 to enable the control.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The isl29023 light sensor driver has supported regulator control,
assign the power supply for isl29023 to enable the control.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the Zodiac Digital Tapping Unit, a VF610 based network device with
5 Ethernet ports. One of these ports supports 1000Base-T2.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The pfla02 SoM has a Micrel KSZ9031RNX ethernet phy connected to the FEC,
which needs RX and TX clock skew settings to compensate for differences
in line length. The skew values are taken from barebox commit
4c65c20f1071 ("ARM: pfla02: Set new ethernet phy tx timings"), which
is based on patches originally provided by Phytec:
TX_CLK line is approx. 54mm longer than other TX lines which adds
a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we
have to add a delay of 0.64ns. We choose 0.78 to have a little gap.
This can be done by setting GTX pad skew value to 11100
Also add a delay for the RX delay lines, needed for the Duallite
variant. => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F.
Cc: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The DA9063 device need the required "interrupt-controller" property as
documented by the bindings [1].
[1] Documentation/devicetree/bindings/mfd/da9063.txt
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This adds the GPIO line names from the schematics to get them displayed
in the debugfs output of each GPIO controller.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
USB_VBUS is a controlled by a Silergy SY6288CCAC-GP 2A Power
Distribution Switch. The name of it's enable GPIO signal is USB_PWR_EN.
VCC5V is supplied by the main power input called PWR_5V_STB. The name of
it's enable GPIO signal is 3V3_5V_EN.
VCC3V3, VCC_DDR3_1V5 and VCCK (the CPU power supply) each use a separate
Silergy SY8089AAC-GP 2A step down regulator. They are all supplied by the
board's main 5V. VCC3V3 and VCC_DDR3_1V5 are fixed regulators while the
voltage of VCCK can be changed by changing it's feedback voltage via
PWM_C.
VCC1V8 is an ABLIC S-1339D18-M5001-GP fixed voltage regulator which is
supplied by VCC3V3.
VCC_RTC is a Global Mixed-mode Technology Inc. G918T12U-GP LDO which. It
is supplied by either VCC3V3 (when the board is powered) or the RTC coin
cell battery.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The INTR32 pin of the IP101GR Ethernet PHY is routed to the GPIOH_3 pad
on the SoC.
Enable the interrupt function of the PHY's INTR32 pin to switch it from
it's default "receive error" mode to "interrupt pin" mode.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
SAR ADC enabled channel 8 can be used to measure the chip temperature.
This can be made available to the hwmon subsystem by using iio-hwmon.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
SAR ADC enabled channel 8 can be used to measure the chip temperature.
This can be made available to the hwmon subsystem by using iio-hwmon.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
SAR ADC enabled channel 8 can be used to measure the chip temperature.
This can be made available to the hwmon subsystem by using iio-hwmon.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The SAR ADC can measure the chip temperature of the SoC. This only
works if the chip is calibrated and if the calibration data is written
to the correct registers. The calibration data is stored in the upper
two bytes of eFuse offset 0x1f4.
This adds the eFuse cell for the temperature calibration data and
passes it to the SAR ADC. We also need to pass the HHI sysctrl node to
the SAR ADC because the 4th TSC (temperature sensor calibration
coefficient) bit is stored in the HHI region (unlike bits [3:0] which
are stored directly inside the SAR ADC's register area).
On boards that have the SAR ADC enabled channel 8 can be used to
measure the chip temperature.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The SAR ADC can measure the chip temperature of the SoC. This only
works if the chip is calibrated and if the calibration data is written
to the correct registers. The calibration data is stored in the upper
two bytes of eFuse offset 0x1f4.
This adds the eFuse cell for the temperature calibration data and
passes it to the SAR ADC. We also need to pass the HHI sysctrl node to
the SAR ADC because the 4th TSC (temperature sensor calibration
coefficient) bit is stored in the HHI region (unlike bits [3:0] which
are stored directly inside the SAR ADC's register area).
On boards that have the SAR ADC enabled channel 8 can be used to
measure the chip temperature.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The SAR ADC on Meson8m2 is slightly different compared to Meson8. The
ADC functionality is identical but the calibration of the internal
thermal sensor is different.
Use the Meson8m2 specific compatible so the temperature sensor is
calibrated correctly on boards using the Meson8m2 SoC.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The clock controller on Meson8/Meson8m2 and Meson8b is part of a
register region called "HHI". This register area contains more
functionality than just a clock controller:
- the clock controller
- some reset controller bits
- temperature sensor calibration data (on Meson8b and Meson8m2 only)
- HDMI controller
Allow access to this HHI register area as "system controller". Also
migrate the Meson8 and Meson8b clock controllers to this new node.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
According to the Odroid-C1+ schematics the Ethernet TXD1 signal is
routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6.
The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and
TXD1 can be routed to DIF_2_N instead.
The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both
configured as Ethernet TXD0 and TXD1 data lines in meson8b.dtsi. At the
same time eth_txd1_0 (GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured
as TXD0 and TXD1 data lines as well.
This results in a bad Ethernet receive performance. Presumably this is
due to the eth_txd0 and eth_txd1 signal being routed to the wrong pins.
As a result of that data can only be transmitted on eth_txd2 and
eth_txd3. However, I have no scope to fully confirm this assumption.
The vendor u-boot sources for Odroid-C1 use the following Ethernet
pinmux configuration:
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f);
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000);
This translates to the following pin groups in the mainline kernel:
- register 6 bit 0: eth_rxd1 (DIF_0_P)
- register 6 bit 1: eth_rxd0 (DIF_0_N)
- register 6 bit 2: eth_rx_dv (DIF_1_P)
- register 6 bit 3: eth_rx_clk (DIF_1_N)
- register 6 bit 6: eth_tx_en (DIF_3_P)
- register 6 bit 8: eth_ref_clk (DIF_3_N)
- register 6 bit 9: eth_mdc (DIF_4_P)
- register 6 bit 10: eth_mdio_en (DIF_4_N)
- register 6 bit 11: eth_tx_clk (GPIOH_9)
- register 6 bit 12: eth_txd2 (GPIOH_8)
- register 6 bit 13: eth_txd3 (GPIOH_7)
- register 7 bit 20: eth_txd0_0 (GPIOH_6)
- register 7 bit 21: eth_txd1_0 (GPIOH_5)
- register 7 bit 22: eth_rxd3 (DIF_2_P)
- register 7 bit 23: eth_rxd2 (DIF_2_N)
Drop the eth_txd0_1 and eth_txd1_1 groups from eth_rgmii_pins to fix the
Ethernet transmit performance on Odroid-C1. Also add the eth_rxd2 and
eth_rxd3 groups so we don't rely on the bootloader to set them up.
iperf3 statistics before this change:
- transmitting from Odroid-C1: 741 Mbits/sec (0 retries)
- receiving on Odroid-C1: 199 Mbits/sec (1713 retries)
iperf3 statistics after this change:
- transmitting from Odroid-C1: 667 Mbits/sec (0 retries)
- receiving on Odroid-C1: 750 Mbits/sec (0 retries)
Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Emiliano Ingrassia <ingrassia@epigenesys.com>
Cc: Linus Lüssing <linus.luessing@c0d3.blue>
Tested-by: Emiliano Ingrassia <ingrassia@epigenesys.com>
Reviewed-by: Emiliano Ingrassia <ingrassia@epigenesys.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the stmpe-adc DT node as found on Toradex iMX6 modules
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
