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Previously, patches have been added to limit the reported count of SATA
ports for asm1064 and asm1166 SATA controllers, as those controllers do
report more ports than physically having.
While it is allowed to report more ports than physically having in CAP.NP,
it is not allowed to report more ports than physically having in the PI
(Ports Implemented) register, which is what these HBAs do.
(This is a AHCI spec violation.)
Unfortunately, it seems that the PMP implementation in these ASMedia HBAs
is also violating the AHCI and SATA-IO PMP specification.
What these HBAs do is that they do not report that they support PMP
(CAP.SPM (Supports Port Multiplier) is not set).
Instead, they have decided to add extra "virtual" ports in the PI register
that is used if a port multiplier is connected to any of the physical
ports of the HBA.
Enumerating the devices behind the PMP as specified in the AHCI and
SATA-IO specifications, by using PMP READ and PMP WRITE commands to the
physical ports of the HBA is not possible, you have to use the "virtual"
ports.
This is of course bad, because this gives us no way to detect the device
and vendor ID of the PMP actually connected to the HBA, which means that
we can not apply the proper PMP quirks for the PMP that is connected to
the HBA.
Limiting the port map will thus stop these controllers from working with
SATA Port Multipliers.
This patch reverts both patches for asm1064 and asm1166, so old behavior
is restored and SATA PMP will work again, but it will also reintroduce the
(minutes long) extra boot time for the ASMedia controllers that do not
have a PMP connected (either on the PCIe card itself, or an external PMP).
However, a longer boot time for some, is the lesser evil compared to some
other users not being able to detect their drives at all.
Fixes: 0077a504e1 ("ahci: asm1166: correct count of reported ports")
Fixes: 9815e39617 ("ahci: asm1064: correct count of reported ports")
Cc: stable@vger.kernel.org
Reported-by: Matt <cryptearth@googlemail.com>
Signed-off-by: Conrad Kostecki <conikost@gentoo.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
[cassel: rewrote commit message]
Signed-off-by: Niklas Cassel <cassel@kernel.org>
- Do not enable LPM for external ports (hotplug-capable ports or eSATA
ports), as the HBA will not be able to detect hot plug removal events
when LPM is enabled. (from me)
- Drop the board type board_ahci_low_power. Now when we make sure that we
won't enable LPM for external ports, we can always set the LPM policy to
CONFIG_SATA_MOBILE_LPM_POLICY for internal ports. There is thus no
longer any need for the board type board_ahci_low_power, so it can be
removed. (As before, LPM features not supported by the HBA and/or the
device will not be enabled, regardless of the LPM policy Kconfig.)
(from Mario Limonciello)
Note that the default CONFIG_SATA_MOBILE_LPM_POLICY value is still 0
(which will not try to enable any LPM features), however, most Linux
distributions override this and set it to 3 (Medium power with DIPM).
We intend to change the default to 3 in the coming cycles, but we will
wait a cycle or two.
- Add board type board_ahci_pcs_quirk and make all legacy Intel platforms
use it. The Intel PCS quirk was being applied to basically all Intel
platforms, which caused some issues (the device failing to come back
after a reset), when being applied to newer Intel platforms where it
shouldn't have been applied. Add board type board_ahci_pcs_quirk and
make legacy Intel platforms use it. New platforms can be added using
board type board_ahci (which will not have the quirk applied).
(from me)
- Rename board_ahci_nosntf to board_ahci_pcs_quirk_no_sntf to more clearly
highlight that it applies two different quirks. (from me)
- Modify the ahci_broken_devslp() quirk to be implemented like all the
other quirks (i.e. define a board type for the quirk). (from me)
- Drop unused board_ahci_noncq board type. (from me)
- Rename board_ahci_nomsi to board_ahci_no_msi to match the other board
types. (from me)
- Make pata_parport_bus_type const. (from Ricardo B. Marliere)
- Remove at91 compact flash device tree binding. (The binding is not used
by any driver.) (from Hari Prasath Gujulan Elango)
- Convert MediaTek device tree binding to json-schema.
(from Rafał Miłecki)
- At boot, print the number of implemented ports, instead of printing the
maximum number of ports supported by the HBA silicon. (from me)
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Merge tag 'ata-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
Pull ata updates from Niklas Cassel:
- Do not enable LPM for external ports (hotplug-capable ports or eSATA
ports), as the HBA will not be able to detect hot plug removal events
when LPM is enabled (me)
- Drop the board type board_ahci_low_power. Now when we make sure that
we won't enable LPM for external ports, we can always set the LPM
policy to CONFIG_SATA_MOBILE_LPM_POLICY for internal ports. There is
thus no longer any need for the board type board_ahci_low_power, so
it can be removed. (As before, LPM features not supported by the HBA
and/or the device will not be enabled, regardless of the LPM policy
Kconfig) (Mario Limonciello)
Note that the default CONFIG_SATA_MOBILE_LPM_POLICY value is still 0
(which will not try to enable any LPM features), however, most Linux
distributions override this and set it to 3 (Medium power with DIPM).
We intend to change the default to 3 in the coming cycles, but we
will wait a cycle or two.
- Add board type board_ahci_pcs_quirk and make all legacy Intel
platforms use it. The Intel PCS quirk was being applied to basically
all Intel platforms, which caused some issues (the device failing to
come back after a reset), when being applied to newer Intel platforms
where it shouldn't have been applied.
New platforms can be added using board type board_ahci, which will
not have the quirk applied (me)
- Rename board_ahci_nosntf to board_ahci_pcs_quirk_no_sntf to more
clearly highlight that it applies two different quirks (me)
- Modify the ahci_broken_devslp() quirk to be implemented like all the
other quirks (i.e. define a board type for the quirk) (me)
- Drop unused board_ahci_noncq board type (me)
- Rename board_ahci_nomsi to board_ahci_no_msi to match the other board
types (me)
- Make pata_parport_bus_type const (Ricardo B. Marliere)
- Remove at91 compact flash device tree binding. (The binding is not
used by any driver.) (from Hari Prasath Gujulan Elango)
- Convert MediaTek device tree binding to json-schema (Rafał Miłecki)
- At boot, print the number of implemented ports, instead of printing
the maximum number of ports supported by the HBA silicon (me)
* tag 'ata-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux:
ahci: print the number of implemented ports
dt-bindings: ata: convert MediaTek controller to the json-schema
ahci: rename board_ahci_nomsi
ahci: drop unused board_ahci_noncq
ahci: clean up ahci_broken_devslp quirk
ahci: rename board_ahci_nosntf
ahci: clean up intel_pcs_quirk
ata: ahci: Drop low power policy board type
ata: ahci: do not enable LPM on external ports
ata: ahci: drop hpriv param from ahci_update_initial_lpm_policy()
ata: ahci: a hotplug capable port is an external port
ata: ahci: move marking of external port earlier
dt-bindings: ata: atmel: remove at91 compact flash documentation
ata: pata_parport: make pata_parport_bus_type const
The ASM1064 SATA host controller always reports wrongly,
that it has 24 ports. But in reality, it only has four ports.
before:
ahci 0000:04:00.0: SSS flag set, parallel bus scan disabled
ahci 0000:04:00.0: AHCI 0001.0301 32 slots 24 ports 6 Gbps 0xffff0f impl SATA mode
ahci 0000:04:00.0: flags: 64bit ncq sntf stag pm led only pio sxs deso sadm sds apst
after:
ahci 0000:04:00.0: ASM1064 has only four ports
ahci 0000:04:00.0: forcing port_map 0xffff0f -> 0xf
ahci 0000:04:00.0: SSS flag set, parallel bus scan disabled
ahci 0000:04:00.0: AHCI 0001.0301 32 slots 24 ports 6 Gbps 0xf impl SATA mode
ahci 0000:04:00.0: flags: 64bit ncq sntf stag pm led only pio sxs deso sadm sds apst
Signed-off-by: "Andrey Jr. Melnikov" <temnota.am@gmail.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
The naming format of the board_ahci_no* boards are:
board_ahci_no_debounce_delay
board_ahci_pcs_quirk_no_devslp
board_ahci_pcs_quirk_no_sntf
Rename board_ahci_nomsi to board_ahci_no_msi to match the other boards.
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Since commit 66a7cbc303 ("ahci: disable MSI instead of NCQ on Samsung
pci-e SSDs on macbooks") there is not a single entry in ahci_pci_tbl
which uses board_ahci_noncq.
Since this is dead code, let's remove it.
We cannot remove AHCI_HFLAG_NO_NCQ, as this flag is still used by other
boards.
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Most quirks are applied using a specific board type board_ahci_no*
(e.g. board_ahci_nomsi, board_ahci_noncq), which then sets a flag
representing the specific quirk.
ahci_pci_tbl (which is the table of all supported PCI devices), then
uses that board type for the PCI vendor and device IDs which need to
be quirked.
The ahci_broken_devslp quirk is not implemented in this standard way.
Modify the ahci_broken_devslp quirk to be implemented like the other
quirks. This way, we will not have the same PCI device and vendor ID
scattered over ahci.c. It will simply be defined in a single location.
Suggested-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Commit 7edbb60592 ("ahci: clean up intel_pcs_quirk") added a new board
type (board_ahci_pcs_quirk) which applies the Intel PCS quirk for legacy
platforms. However, it also modified board_ahci_avn and board_ahci_nosntf
to apply the same quirk.
board_ahci_avn is defined under the label:
/* board IDs for specific chipsets in alphabetical order */
This is a board for a specific chipset, so the naming is perfectly fine.
(The name does not need to be suffixed with _pcs_quirk, since all
controllers for this chipset require the quirk to be applied).
board_ahci_nosntf is defined under the label:
/* board IDs by feature in alphabetical order */
This is a board for a specific feature/quirk. However, it is used to
apply two different quirks.
Rename board_ahci_nosntf to more clearly highlight that this board ID
applies two different quirks.
Fixes: 7edbb60592 ("ahci: clean up intel_pcs_quirk")
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
The comment in front of board_ahci_pcs7 is completely wrong.
It claims that board_ahci_pcs7 is needing the quirk, but in fact,
the logic implemented in ahci_intel_pcs_quirk() is the exact opposite,
only board_ahci_pcs7 is _excluded_ from the quirk.
This way of implementing a quirk is unconventional in several ways:
First of all because it has a board ID for which the quirk should _not_ be
applied (board_ahci_pcs7), instead of the usual way where we have a board
ID for which the quirk should be applied.
The second reason is that other than only excluding board_ahci_pcs7 from
the quirk, PCI devices that make use of the generic entry in ahci_pci_tbl
(which matches on AHCI class code) are also excluded.
This can of course lead to very subtle breakage, and did indeed do so in:
commit 104ff59af7 ("ata: ahci: Add Tiger Lake UP{3,4} AHCI controller"),
which added an explicit entry with board_ahci_low_power to ahci_pci_tbl.
This caused many users to complain that their SATA drives disappeared.
The logical assumption was of course that the issue was related to LPM,
and was therefore reverted in commit 6210038aea ("ata: ahci: Revert
"ata: ahci: Add Tiger Lake UP{3,4} AHCI controller"").
It took a lot of time to figure out that this was all completely unrelated
to LPM, and was instead caused by an unconventional Intel quirk.
Clean up the quirk so that it behaves like other quirks, i.e. define a
board where the quirk is applied. Platforms that were using
board_ahci_pcs7 are converted to use board_ahci, this is safe since the
boards were identical, and board_ahci_pcs7 did not define any custom
port_ops.
This way, new Intel platforms can be added using the correct "board_ahci"
board, without getting any unexpected quirks applied.
This means that we currently have some modern platforms defined that are
using the Intel PCS quirk, but that is identical to the behavior that
was there before this commit.
No functional changes intended.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=217114
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
The low power policy board type was introduced to allow systems
to get into deep states reliably. Before it was introduced `min_power`
was causing problems for a number of drives. New power policies
`min_power_with_partial` and `med_power_with_dipm` have been introduced
which provide a more stable baseline for systems.
Tested-by: Damien Le Moal <dlemoal@kernel.org>
Tested-by: Jian-Hong Pan <jhp@endlessos.org>
Acked-by: Jian-Hong Pan <jhp@endlessos.org>
Acked-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Suggested-by: Christoph Hellwig <hch@infradead.org>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
[cassel: rebase patch and fix trivial conflicts]
Signed-off-by: Niklas Cassel <cassel@kernel.org>
AHCI 1.3.3, 7.3.1.1 Software Flow for Hot Plug Removal Detection states:
"To reliably detect hot plug removals, software must disable interface
power management.
Software should perform the following initialization on a port after a
device is attached:
-Set PxSCTL.IPM to 3h to disable interface power management state
transitions.
-Set PxCMD.ALPE to ‘0’ to disable aggressive power management.
-Ensure PxIE.PRCE is set to ‘1’ to enable interrupts on hot plug removals.
-Disable device initiated interface power management by issuing the
appropriate SET FEATURES command."
Further, AHCI 1.3.3, 7.3 Native Hot Plug Support states:
"The HBA shall set the PxSERR.DIAG.X bit to ‘1’ when a COMINIT is received
from the device. Hot plug insertions are detected via the PxIS.PCS bit
that directly reflects the PxSERR.DIAG.X bit. The HBA shall set the
PxSERR.DIAG.N bit to ‘1’ when the HBA’s internal PhyRdy signal changes
state.
Hot plug removals are detected via the PxIS.PRCS bit that directly
reflects the PxSERR.DIAG.N bit. Note that PxSERR.DIAG.N is also set
to ‘1’ on insertions and during interface power management entry/exit."
ahci_set_lpm() already disables the PxIS.PRCS interrupt if setting a
LPM policy != ATA_LPM_MAX_POWER, so we cannot detect hot plug removals
when LPM policy != ATA_LPM_MAX_POWER.
We do have PxIS.PCS interrupt enabled even for LPM policy !=
ATA_LPM_MAX_POWER, so we should theoretically still be able to detect
hot plug insertions even when LPM is enabled.
However, in practise, for LPM policy ATA_LPM_MED_POWER_WITH_DIPM,
ATA_LPM_MIN_POWER_WITH_PARTIAL, and ATA_LPM_MIN_POWER, if there is
no link enabled, sata_link_scr_lpm() will set SControl.DET = 0x4,
which will transition the port to the "P:Offline" state.
The P:Offline mode is described in SATA Gold 3.5a:
4.1.1.103 Phy offline:
"In this mode the host Phy is forced off and the host Phy does not
recognize nor respond to COMINIT or COMWAKE. This mode is entered by
setting the DET field of the SControl register to 0100b. This is a
mechanism for the host to turn off its Phy."
So in the P:Offline state the PHY does not recognize the unsolicited
COMINIT which is sent on a hot plug insertion.
While we could change sata_link_scr_lpm() to never power off an external
port for LPM policy != ATA_LPM_MAX_POWER (in order be able to handle hot
plug insertions), we still would not be able to handle hot plug removals.
Thus, simply modify ahci_update_initial_lpm_policy() to not enable LPM if
the port advertises itself as an external port, as this function is
already being used to set/override the initial LPM policy.
Tested-by: Damien Le Moal <dlemoal@kernel.org>
Tested-by: Jian-Hong Pan <jhp@endlessos.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
There is no need for ahci_update_initial_lpm_policy() to take hpriv as a
parameter, it can easily be derived from the ata_port.
Tested-by: Damien Le Moal <dlemoal@kernel.org>
Tested-by: Jian-Hong Pan <jhp@endlessos.org>
Acked-by: Jian-Hong Pan <jhp@endlessos.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
A hotplug capable port is an external port, so mark it as such.
We even say this ourselves in libata-scsi.c:
/* set scsi removable (RMB) bit per ata bit, or if the
* AHCI port says it's external (Hotplug-capable, eSATA).
*/
This also matches the terminology used in AHCI 1.3.1
(the keyword to search for is "externally accessible").
Tested-by: Damien Le Moal <dlemoal@kernel.org>
Tested-by: Jian-Hong Pan <jhp@endlessos.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Move the marking of an external port earlier in the call chain.
This is needed for further cleanups.
No functional change intended.
Tested-by: Damien Le Moal <dlemoal@kernel.org>
Tested-by: Jian-Hong Pan <jhp@endlessos.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
ASMedia have confirmed that all ASM106x parts currently listed in
ahci_pci_tbl[] suffer from the 43-bit DMA address limitation that we ran
into on the ASM1061, and therefore, we need to apply the quirk added by
commit 20730e9b27 ("ahci: add 43-bit DMA address quirk for ASMedia
ASM1061 controllers") to the other supported ASM106x parts as well.
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/linux-ide/ZbopwKZJAKQRA4Xv@x1-carbon/
Signed-off-by: Lennert Buytenhek <kernel@wantstofly.org>
[cassel: add link to ASMedia confirmation email]
Signed-off-by: Niklas Cassel <cassel@kernel.org>
With one of the on-board ASM1061 AHCI controllers (1b21:0612) on an
ASUSTeK Pro WS WRX80E-SAGE SE WIFI mainboard, a controller hang was
observed that was immediately preceded by the following kernel
messages:
ahci 0000:28:00.0: Using 64-bit DMA addresses
ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00000 flags=0x0000]
ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00300 flags=0x0000]
ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00380 flags=0x0000]
ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00400 flags=0x0000]
ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00680 flags=0x0000]
ahci 0000:28:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0035 address=0x7fffff00700 flags=0x0000]
The first message is produced by code in drivers/iommu/dma-iommu.c
which is accompanied by the following comment that seems to apply:
/*
* Try to use all the 32-bit PCI addresses first. The original SAC vs.
* DAC reasoning loses relevance with PCIe, but enough hardware and
* firmware bugs are still lurking out there that it's safest not to
* venture into the 64-bit space until necessary.
*
* If your device goes wrong after seeing the notice then likely either
* its driver is not setting DMA masks accurately, the hardware has
* some inherent bug in handling >32-bit addresses, or not all the
* expected address bits are wired up between the device and the IOMMU.
*/
Asking the ASM1061 on a discrete PCIe card to DMA from I/O virtual
address 0xffffffff00000000 produces the following I/O page faults:
vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000000 flags=0x0010]
vfio-pci 0000:07:00.0: AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0021 address=0x7ff00000500 flags=0x0010]
Note that the upper 21 bits of the logged DMA address are zero. (When
asking a different PCIe device in the same PCIe slot to DMA to the
same I/O virtual address, we do see all the upper 32 bits of the DMA
address as 1, so this is not an issue with the chipset or IOMMU
configuration on the test system.)
Also, hacking libahci to always set the upper 21 bits of all DMA
addresses to 1 produces no discernible effect on the behavior of the
ASM1061, and mkfs/mount/scrub/etc work as without this hack.
This all strongly suggests that the ASM1061 has a 43 bit DMA address
limit, and this commit therefore adds a quirk to deal with this limit.
This issue probably applies to (some of) the other supported ASMedia
parts as well, but we limit it to the PCI IDs known to refer to
ASM1061 parts, as that's the only part we know for sure to be affected
by this issue at this point.
Link: https://lore.kernel.org/linux-ide/ZaZ2PIpEId-rl6jv@wantstofly.org/
Signed-off-by: Lennert Buytenhek <kernel@wantstofly.org>
[cassel: drop date from error messages in commit log]
Signed-off-by: Niklas Cassel <cassel@kernel.org>
The ASM1166 SATA host controller always reports wrongly,
that it has 32 ports. But in reality, it only has six ports.
This seems to be a hardware issue, as all tested ASM1166
SATA host controllers reports such high count of ports.
Example output: ahci 0000:09:00.0: AHCI 0001.0301
32 slots 32 ports 6 Gbps 0xffffff3f impl SATA mode.
By adjusting the port_map, the count is limited to six ports.
New output: ahci 0000:09:00.0: AHCI 0001.0301
32 slots 32 ports 6 Gbps 0x3f impl SATA mode.
Closes: https://bugzilla.kernel.org/show_bug.cgi?id=211873
Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218346
Signed-off-by: Conrad Kostecki <conikost@gentoo.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Intel Alder Lake-P AHCI controller needs to be added to the mobile
chipsets list in order to have link power management enabled. Without
this the CPU cannot enter lower power C-states making idle power
consumption high.
Cc: Koba Ko <koba.ko@canonical.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Add support for PCIe SATA adapter cards based on Asmedia 2116 controllers.
These cards can provide up to 10 SATA ports on PCIe card.
Signed-off-by: Szuying Chen <Chloe_Chen@asmedia.com.tw>
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
In AHCI 1.3.1, the register description for CAP.SSC:
"When cleared to ‘0’, software must not allow the HBA to initiate
transitions to the Slumber state via agressive link power management nor
the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port
must be programmed to disallow device initiated Slumber requests."
In AHCI 1.3.1, the register description for CAP.PSC:
"When cleared to ‘0’, software must not allow the HBA to initiate
transitions to the Partial state via agressive link power management nor
the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port
must be programmed to disallow device initiated Partial requests."
Ensure that we always set the corresponding bits in PxSCTL.IPM, such that
a device is not allowed to initiate transitions to power states which are
unsupported by the HBA.
DevSleep is always initiated by the HBA, however, for completeness, set the
corresponding bit in PxSCTL.IPM such that agressive link power management
cannot transition to DevSleep if DevSleep is not supported.
sata_link_scr_lpm() is used by libahci, ata_piix and libata-pmp.
However, only libahci has the ability to read the CAP/CAP2 register to see
if these features are supported. Therefore, in order to not introduce any
regressions on ata_piix or libata-pmp, create flags that indicate that the
respective feature is NOT supported. This way, the behavior for ata_piix
and libata-pmp should remain unchanged.
This change is based on a patch originally submitted by Runa Guo-oc.
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Fixes: 1152b2617a ("libata: implement sata_link_scr_lpm() and make ata_dev_set_feature() global")
Cc: stable@vger.kernel.org
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Elkhart Lake is the successor of Apollo Lake and Gemini Lake. These
CPUs and their PCHs are used in mobile and embedded environments.
With this patch I suggest that Elkhart Lake SATA controllers [1] should
use the default LPM policy for mobile chipsets.
The disadvantage of missing hot-plug support with this setting should
not be an issue, as those CPUs are used in embedded environments and
not in servers with hot-plug backplanes.
We discovered that the Elkhart Lake SATA controllers have been missing
in ahci.c after a customer reported the throttling of his SATA SSD
after a short period of higher I/O. We determined the high temperature
of the SSD controller in idle mode as the root cause for that.
Depending on the used SSD, we have seen up to 1.8 Watt lower system
idle power usage and up to 30°C lower SSD controller temperatures in
our tests, when we set med_power_with_dipm manually. I have provided a
table showing seven different SATA SSDs from ATP, Intel/Solidigm and
Samsung [2].
Intel lists a total of 3 SATA controller IDs (4B60, 4B62, 4B63) in [1]
for those mobile PCHs.
This commit just adds 0x4b63 as I do not have test systems with 0x4b60
and 0x4b62 SATA controllers.
I have tested this patch with a system which uses 0x4b63 as SATA
controller.
[1] https://sata-io.org/product/8803
[2] https://www.thomas-krenn.com/en/wiki/SATA_Link_Power_Management#Example_LES_v4
Signed-off-by: Werner Fischer <devlists@wefi.net>
Cc: stable@vger.kernel.org
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
sata_deb_timing_{hotplug|long|normal}[] store 'unsigned long' debounce
timeouts in ms, while sata_link_debounce() eventually uses those timeouts
by calling ata_{deadline|msleep}( which take just 'unsigned int'. Change
the debounce timeout table element's type to 'unsigned int' -- all these
timeouts happily fit into 'unsigned int'...
Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Make it explicit that ATA host templates are not modified.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com> (for DWC AHCI SATA)
Reviewed-by: John Garry <john.g.garry@oracle.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com> (for Tegra)
Cc: Christoph Hellwig <hch@lst.de>
Cc: Ming Lei <ming.lei@redhat.com>
Cc: Hannes Reinecke <hare@suse.de>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mike Christie <michael.christie@oracle.com>
Signed-off-by: Bart Van Assche <bvanassche@acm.org>
Link: https://lore.kernel.org/r/20230322195515.1267197-5-bvanassche@acm.org
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Commit 104ff59af7 ("ata: ahci: Add Tiger Lake UP{3,4} AHCI
controller") enabled low power mode for the Tiger Lake AHIC adapter in
the author system but created regressions for others. Revert this patch
for now until a better solution is found to make this adapter
eco-friendly.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=217114
CC: stable@vger.kernel.org
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Mark the Tiger Lake UP{3,4} AHCI controller as "low_power". This enables
S0ix to work out of the box. Otherwise this isn't working unless the
user manually sets /sys/class/scsi_host/*/link_power_management_policy.
Intel lists a total of 4 SATA controller IDs in [1] for those mobile
PCHs. This commit just adds the "AHCI" variant since I only tested
those.
[1]: https://cdrdv2.intel.com/v1/dl/getContent/631119
Signed-off-by: Simon Gaiser <simon@invisiblethingslab.com>
CC: stable@vger.kernel.org
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Since kernel 5.3.4 my laptop (ICH8M controller) does not see Kingston
SV300S37A60G SSD disk connected into a SATA connector on wake from
suspend. The problem was introduced in c312ef1763 ("libata/ahci: Drop
PCS quirk for Denverton and beyond"): the quirk is not applied on wake
from suspend as it originally was.
It is worth to mention the commit contained another bug: the quirk is
not applied at all to controllers which require it. The fix commit
09d6ac8dc5 ("libata/ahci: Fix PCS quirk application") landed in 5.3.8.
So testing my patch anywhere between commits c312ef1763 and
09d6ac8dc5 is pointless.
Not all disks trigger the problem. For example nothing bad happens with
Western Digital WD5000LPCX HDD.
Test hardware:
- Acer 5920G with ICH8M SATA controller
- sda: some SATA HDD connnected into the DVD drive IDE port with a
SATA-IDE caddy. It is a boot disk
- sdb: Kingston SV300S37A60G SSD connected into the only SATA port
Sample "dmesg --notime | grep -E '^(sd |ata)'" output on wake:
sd 0:0:0:0: [sda] Starting disk
sd 2:0:0:0: [sdb] Starting disk
ata4: SATA link down (SStatus 4 SControl 300)
ata3: SATA link down (SStatus 4 SControl 300)
ata1.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out
ata1.00: ACPI cmd ef/03:42:00:00:00:a0 (SET FEATURES) filtered out
ata1: FORCE: cable set to 80c
ata5: SATA link down (SStatus 0 SControl 300)
ata3: SATA link down (SStatus 4 SControl 300)
ata3: SATA link down (SStatus 4 SControl 300)
ata3.00: disabled
sd 2:0:0:0: rejecting I/O to offline device
ata3.00: detaching (SCSI 2:0:0:0)
sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_NO_CONNECT
driverbyte=DRIVER_OK
sd 2:0:0:0: [sdb] Synchronizing SCSI cache
sd 2:0:0:0: [sdb] Synchronize Cache(10) failed: Result:
hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK
sd 2:0:0:0: [sdb] Stopping disk
sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_BAD_TARGET
driverbyte=DRIVER_OK
Commit c312ef1763 dropped ahci_pci_reset_controller() which internally
calls ahci_reset_controller() and applies the PCS quirk if needed after
that. It was called each time a reset was required instead of just
ahci_reset_controller(). This patch puts the function back in place.
Fixes: c312ef1763 ("libata/ahci: Drop PCS quirk for Denverton and beyond")
Signed-off-by: Adam Vodopjan <grozzly@protonmail.com>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Nothing in this file needs anything from linux/msi.h
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Cc: linux-ide@vger.kernel.org
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
The port base address may be required even before the ata_host instance is
initialized and activated, for instance in the ahci_save_initial_config()
method which we are about to update (consider this modification as a
preparation for that one). Seeing the __ahci_port_base() function isn't
used much it's the best candidate to provide the required functionality.
So let's convert it to accepting the ahci_host_priv structure pointer.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Currently there are four port-map-related fields declared in the
ahci_host_priv structure and used to setup the HBA ports mapping. First
the ports-mapping is read from the PI register and immediately stored in
the saved_port_map field. If forced_port_map is initialized with non-zero
value then its value will have greater priority over the value read from
PI, thus it will override the saved_port_map field. That value will be
then masked by a non-zero mask_port_map field and after some sanity checks
it will be stored in the ahci_host_priv.port_map field as a final port
mapping.
As you can see the logic is a bit too complicated for such a simple task.
We can freely get rid from at least one of the fields with no change to
the implemented semantic. The force_port_map field can be replaced with
taking non-zero saved_port_map value into account. So if saved_port_map is
pre-initialized by the low level drivers (platform drivers) then it will
have greater priority over the value read from PI register and will be
used as actual HBA ports mapping later on. Thus the ports map forcing task
will be just transferred from force_port_map to the saved_port_map field.
This modification will perfectly fit into the feature of having OF-based
initialization of the HW-init HBA CSR fields we are about to introduce in
the next commit.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
The ACPI_FADT_LOW_POWER_S0 flag merely means that it is better to
use low-power S0 idle on the given platform than S3 (provided that
the latter is supported) and it doesn't preclude using either of
them (which of them will be used depends on the choices made by user
space).
For this reason, there is no benefit from checking that flag in
ahci_update_initial_lpm_policy().
First off, it cannot be a bug to do S3 with policy set to either
ATA_LPM_MIN_POWER_WITH_PARTIAL or ATA_LPM_MIN_POWER, because S3 can be
used on systems with ACPI_FADT_LOW_POWER_S0 set and it must work if
really supported, so the ACPI_FADT_LOW_POWER_S0 check is not needed to
protect the S3-capable systems from failing.
Second, suspend-to-idle can be carried out on a system with
ACPI_FADT_LOW_POWER_S0 unset and it is expected to work, so if setting
policy to either ATA_LPM_MIN_POWER_WITH_PARTIAL or ATA_LPM_MIN_POWER is
needed to handle that case correctly, it should be done regardless of
the ACPI_FADT_LOW_POWER_S0 value.
Accordingly, replace the ACPI_FADT_LOW_POWER_S0 check in
ahci_update_initial_lpm_policy() with pm_suspend_default_s2idle()
which is more general and also takes the user's preference into
account and drop the CONFIG_ACPI #ifdef around it that is not necessary
any more.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Intel server platforms that support 'RAID', i.e. have platform firmware
support for software-RAID metadata + features that the kernel also
understands, maintain the same device-ids for RAID from generation to
generation. This is in contrast to client platforms that have tended to
roll new device-ids every platform generation. However, even though
server platform keep the ids there are still unique device-ids per
controller instance. To date there have only been 2 controllers on these
platforms, but platforms code named Emmitsburg add a third controller.
Add the device-id for this third controller and collect it with the
other generic server RAID ids.
As mentioned here [1], the pain of continuing add new and different
device-ids for RAID mode to this file [2] has been heard. Ideally this
device-id would not matter and the class code would remain
PCI_CLASS_STORAGE_SATA_AHCI regardless of the RAID mode, but other
operating systems depend on the class code *not* being AHCI when the
device is in RAID mode. That said, going forward there is little reason
for new server RAID ids to be added as they can simply reuse one of the
existing ids even for a new controller. Server software RAID features
continue to be supported on Linux. Client software RAID features
continue to be not supported and the recommendation there remains to set
the device to AHCI mode in platform firmware.
Link: https://lore.kernel.org/all/8e61fb0104422e8d70701e2ddc7b1ca53f009797.camel@intel.com [1]
Link: https://lore.kernel.org/all/20201119165022.GA3582@infradead.org/ [2]
Cc: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
CONFIG_SATA_LPM_MOBILE_POLICY was renamed to CONFIG_SATA_LPM_POLICY in
commit 4dd4d3deb5 ("ata: ahci: Rename CONFIG_SATA_LPM_MOBILE_POLICY
configuration item").
This can potentially cause problems as users would invisibly lose
configuration policy defaults when they built the new kernel. To
avoid such problems, switch back to the old name (even if it's wrong).
Suggested-by: Christoph Hellwig <hch@infradead.org>
Suggested-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
`CONFIG_SATA_LPM_MOBILE_POLICY` reflects a configuration to apply only to
mobile chipsets. As some desktop boards may want to use this policy by
default as well, rename the configuration item to `SATA_LPM_POLICY`.
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
`AHCI_HFLAG_IS_MOBILE` designates that a chipset should be using the
default link power management policy from a kernel configuration item.
As desktop chipsets may also be interested in this default policy
configuration, rename the flag to `AHCI_HFLAG_USE_LPM_POLICY` to more
accurately reflect that a chipset doesn't have to be mobile to adopt it.
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
This board definition was originally created for mobile devices to
designate default link power managmeent policy to influence runtime
power consumption.
As this is interesting for more than just mobile designs, rename the
board to `board_ahci_low_power` to make it clear it is about default
policy.
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Add the explicit error and status register fields to 'struct ata_taskfile'
using the anonymous *union*s ('struct ide_taskfile' had that for ages!) and
update the libata taskfile code accordingly. There should be no object code
changes resulting from that...
Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
ata_host_suspend() always returns 0, so the result checks in many drivers
look pointless. Let's make this function return *void* instead of *int*.
Found by Linux Verification Center (linuxtesting.org) with the SVACE static
analysis tool.
Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
The 200 ms delay before debouncing the PHY in `sata_link_resume()` is
not needed for the Marvell 88SE9235.
$ lspci -nn -s 0021:0e:00.0
0021:0e:00.0 SATA controller [0106]: Marvell Technology Group Ltd. 88SE9235 PCIe 2.0 x2 4-port SATA 6 Gb/s Controller [1b4b:9235] (rev 11)
So, remove it using the board_ahci_no_debounce_delay board definition.
Tested on IBM S822LC with current Linux 5.17-rc1:
Currently, without this patch (with 200 ms delay), device probe for ata1
takes 485 ms:
[ 3.358158] ata1: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3fe881000100 irq 39
[ 3.358175] ata2: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3fe881000180 irq 39
[ 3.358191] ata3: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3fe881000200 irq 39
[ 3.358207] ata4: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3fe881000280 irq 39
[…]
[ 3.677542] ata3: SATA link down (SStatus 0 SControl 300)
[ 3.677719] ata4: SATA link down (SStatus 0 SControl 300)
[ 3.839242] ata2: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 3.839828] ata2.00: ATA-10: ST1000NX0313 00LY266 00LY265IBM, BE33, max UDMA/133
[ 3.840029] ata2.00: 1953525168 sectors, multi 0: LBA48 NCQ (depth 32), AA
[ 3.841796] ata2.00: configured for UDMA/133
[ 3.843231] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 3.844083] ata1.00: ATA-10: ST1000NX0313 00LY266 00LY265IBM, BE33, max UDMA/133
[ 3.844313] ata1.00: 1953525168 sectors, multi 0: LBA48 NCQ (depth 32), AA
[ 3.846043] ata1.00: configured for UDMA/133
With this patch (no delay) device probe for ata1 takes 273 ms:
[ 3.624259] ata1: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3f e881000100 irq 39
[ 3.624436] ata2: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3f e881000180 irq 39
[ 3.624452] ata3: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3f e881000200 irq 39
[ 3.624468] ata4: SATA max UDMA/133 abar m2048@0x3fe881000000 port 0x3f e881000280 irq 39
[…]
[ 3.731966] ata3: SATA link down (SStatus 0 SControl 300)
[ 3.732069] ata4: SATA link down (SStatus 0 SControl 300)
[ 3.897448] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 3.897678] ata2: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 3.898140] ata1.00: ATA-10: ST1000NX0313 00LY266 00LY265IBM, BE33, max UDMA/133
[ 3.898175] ata2.00: ATA-10: ST1000NX0313 00LY266 00LY265IBM, BE33, max UDMA/133
[ 3.898287] ata1.00: 1953525168 sectors, multi 0: LBA48 NCQ (depth 32), AA
[ 3.898349] ata2.00: 1953525168 sectors, multi 0: LBA48 NCQ (depth 32), AA
[ 3.900070] ata1.00: configured for UDMA/133
[ 3.900166] ata2.00: configured for UDMA/133
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Add support for the AMD A85 FCH (Hudson D4) AHCI adapter.
Since this adapter does not require the default 200 ms debounce delay
in sata_link_resume(), create a new board board_ahci_no_debounce_delay
with the link flag ATA_LFLAG_NO_DEBOUNCE_DELAY, and, for now, configure
the AMD A85 FCH (Hudson D4) to use it. On the ASUS F2A85-M PRO it
reduces the Linux kernel boot time by the expected 200 ms from 787 ms
to 585 ms.
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Cc: Tejun Heo <tj@kernel.org>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Drop pointless VPRINTK() calls for entering and existing interrupt
routines and convert the remaining calls to dev_dbg().
Signed-off-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
To follow the flow of control we should be using tracepoints, as
they will tie in with the actual I/O flow and deliver a better
overview about what it happening.
This patch adds tracepoints for hard reset, soft reset, and postreset
and adds them in the libata-eh control flow.
With that we can drop the reset DPRINTK calls in the various drivers.
Signed-off-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Debugging messages in pci init functions or sg setup are pretty
much pointless, as the workflow pretty much decides what happened.
So drop them.
Signed-off-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
AMD requires that the SATA controller be configured for devsleep in order
for S0i3 entry to work properly.
commit b1a9585cc3 ("ata: ahci: Enable DEVSLP by default on x86 with
SLP_S0") sets up a kernel policy to enable devsleep on Intel mobile
platforms that are using s0ix. Add the PCI ID for the SATA controller in
Green Sardine platforms to extend this policy by default for AMD based
systems using s0i3 as well.
Cc: Nehal-bakulchandra Shah <Nehal-bakulchandra.Shah@amd.com>
BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=214091
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Add support for PCIe SATA expander cards based on ASMedia 1062 + JBM575
controllers.
These cards can provide up to 10 or more SATA ports on one PCIe card.
Signed-off-by: István Pongrácz <pongracz.istvan@gmail.com>
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Intel devices 0x2822, 0x2823, 0x2826 and 0x2827 are already on the list
as Lewisburg AHCI/RAID. They use same configuration except 0x2822 which
has board_ahci_nosntf (for ICH8).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
This patch enables support for Dell S140 and later controllers
that use Intel's PCHs configured as PCI_CLASS_STORAGE_RAID.
Reviewed-by: Mika Westerberg <mika.westerberg@intel.com>
Signed-off-by: Charles Rose <charles.rose@dell.com>
Link: https://lore.kernel.org/r/20210615190801.1744466-1-charles.rose@dell.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
On Hisilicon Kunpeng920, ESP is set to 1 by default for all ports of
SATA controller. In some scenarios, some ports are not external SATA ports,
and it cause disks connected to these ports to be identified as removable
disks. So disable the SXS capability on the software side to prevent users
from mistakenly considering non-removable disks as removable disks and
performing related operations.
Signed-off-by: Xingui Yang <yangxingui@huawei.com>
Signed-off-by: Luo Jiaxing <luojiaxing@huawei.com>
Reviewed-by: John Garry <john.garry@huawei.com>
Link: https://lore.kernel.org/r/1615544676-61926-1-git-send-email-luojiaxing@huawei.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Add Intel Rocket Lake PCH-H RAID PCI IDs to the list of supported
controllers.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Add Intel Comet Lake PCH-U PCI ID to the list of supported controllers.
Set default SATA LPM so the SoC can enter S0ix.
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
