2 Commits

Author	SHA1	Message	Date
AngeloGioacchino Del Regno	8da312d657	clk: mediatek: fhctl: Add support for older fhctl register layout ... The Frequency Hopping Controller (FHCTL) seems to have different versions, as it has a slightly different register layout on some older SoCs like MT6795, MT8173, MT8183 (and others). This driver is indeed compatible with at least some of those older IP revisions, so all we need to do is to add a way to select the right register layout at registration time. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230206100105.861720-2-angelogioacchino.delregno@collabora.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2023-03-13 11:46:23 -07:00
Johnson Wang	d7964de8a8	clk: mediatek: Add new clock driver to handle FHCTL hardware ... To implement frequency hopping and spread spectrum clocking function, we introduce new clock type and APIs to handle FHCTL hardware. Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221121122957.21611-4-johnson.wang@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>	2022-11-29 14:43:07 +08:00