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Author	SHA1	Message	Date
Josh Boyer	c1b78d05b3	[POWERPC] Generalize tsi108 PHY types Add a phy_type field to the tsi108 ethernet structures to indicate which PHY is used on a board. This is derived from the "compatible" property in the ethernet-phy node of the device tree. The default remains the MV88E PHY. Also, convert the setup code to use of_get_mac_address instead of hard coding a lookup for the "address" property in the ethernet node. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>	2007-05-08 11:54:20 +10:00
Zang Roy-r61911	5e123b844a	[PATCH] Add tsi108/9 On Chip Ethernet device driver support Add tsi108/9 on chip Ethernet controller driver support. The driver code collects the feedback of previous posting form the mailing list and gives the update. MPC7448HPC2 platform in arch/powerpc uses tsi108 bridge. The following is a brief description of the Ethernet controller: The Tsi108/9 Ethernet Controller connects Switch Fabric to two independent Gigabit Ethernet ports,E0 and E1. It uses a single Management interface to manage the two physical connection devices (PHYs). Each Ethernet port has its own statistics monitor that tracks and reports key interface statistics. Each port supports a 256-entry hash table for address filtering. In addition, each port is bridged to the Switch Fabric through a 2-Kbyte transmit FIFO and a 4-Kbyte Receive FIFO. Each Ethernet port also has a pair of internal Ethernet DMA channels to support the transmit and receive data flows. The Ethernet DMA channels use descriptors set up in memory, the memory map of the device, and access via the Switch Fabric. The Ethernet Controller’s DMA arbiter handles arbitration for the Switch Fabric. The Controller also has a register bus interface for register accesses and status monitor control. The PMD (Physical Media Device) interface operates in MII, GMII, or TBI modes. The MII mode is used for connecting with 10 or 100 Mbit/s PMDs. The GMII and TBI modes are used to connect with Gigabit PMDs. Internal data flows to and from the Ethernet Controller through the Switch Fabric. Each Ethernet port uses its transmit and receive DMA channels to manage data flows through buffer descriptors that are predefined by the system (the descriptors can exist anywhere in the system memory map). These descriptors are data structures that point to buffers filled with data ready to transmit over Ethernet, or they point to empty buffers ready to receive data from Ethernet. Signed-off-by: Alexandre Bounine <Alexandre.Bounine@tundra.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>	2006-12-02 00:12:03 -05:00

Author

SHA1

Message

Date

Josh Boyer

c1b78d05b3

[POWERPC] Generalize tsi108 PHY types

Add a phy_type field to the tsi108 ethernet structures to indicate which PHY
is used on a board.  This is derived from the "compatible" property in the
ethernet-phy node of the device tree.  The default remains the MV88E PHY.

Also, convert the setup code to use of_get_mac_address instead of hard coding
a lookup for the "address" property in the ethernet node.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>

2007-05-08 11:54:20 +10:00

Zang Roy-r61911

5e123b844a

[PATCH] Add tsi108/9 On Chip Ethernet device driver support

Add tsi108/9 on chip Ethernet controller driver support.

The driver code collects the feedback of previous posting form the mailing
list and gives the update.

MPC7448HPC2 platform in arch/powerpc uses tsi108 bridge.

The following is a brief description of the Ethernet controller:

The Tsi108/9 Ethernet Controller connects Switch Fabric to two independent
Gigabit Ethernet ports,E0 and E1.  It uses a single Management interface to
manage the two physical connection devices (PHYs).  Each Ethernet port has
its own statistics monitor that tracks and reports key interface
statistics.  Each port supports a 256-entry hash table for address
filtering.  In addition, each port is bridged to the Switch Fabric through
a 2-Kbyte transmit FIFO and a 4-Kbyte Receive FIFO.

Each Ethernet port also has a pair of internal Ethernet DMA channels to
support the transmit and receive data flows.  The Ethernet DMA channels use
descriptors set up in memory, the memory map of the device, and access via
the Switch Fabric.  The Ethernet Controller’s DMA arbiter handles
arbitration for the Switch Fabric.  The Controller also has a register bus
interface for register accesses and status monitor control.

The PMD (Physical Media Device) interface operates in MII, GMII, or TBI
modes.  The MII mode is used for connecting with 10 or 100 Mbit/s PMDs.
The GMII and TBI modes are used to connect with Gigabit PMDs.  Internal
data flows to and from the Ethernet Controller through the Switch Fabric.
Each

Ethernet port uses its transmit and receive DMA channels to manage data
flows through buffer descriptors that are predefined by the system (the
descriptors can exist anywhere in the system memory map).  These
descriptors are data structures that point to buffers filled with data
ready to transmit over Ethernet, or they point to empty buffers ready to
receive data from Ethernet.

Signed-off-by: Alexandre Bounine <Alexandre.Bounine@tundra.com>
Signed-off-by: Roy Zang	<tie-fei.zang@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

2006-12-02 00:12:03 -05:00

2 Commits