iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
1,121,570 Commits 104 Branches 1,843 Tags
Commit Graph

5 Commits

Author SHA1 Message Date
Michal Simek
4d79e36718 dt-bindings: pci: xilinx-nwl: Document optional clock property 
Clock property hasn't been documented in binding document but it is used
for quite a long time where clock was specified by commit 9c8a47b484ed
("arm64: dts: xilinx: Add the clock nodes for zynqmp").

Link: https://lore.kernel.org/r/67aa2c189337181bb2d7721fb616db5640587d2a.1624618100.git.michal.simek@xilinx.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
 2021-08-13 15:39:27 +01:00
Bharat Kumar Gogada
1c4422f226 PCI: xilinx-nwl: Add optional "dma-coherent" property 
Add optional dma-coherent property to support coherent PCIe DMA traffic.

Link: https://lore.kernel.org/r/20210222084732.21521-2-bharat.kumar.gogada@xilinx.com
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
 2021-04-07 16:59:23 +01:00
Bjorn Helgaas
96291d5655 PCI: Fix typos and whitespace errors 
Fix various typos and whitespace errors:

  s/Synopsis/Synopsys/
  s/Designware/DesignWare/
  s/Keystine/Keystone/
  s/gpio/GPIO/
  s/pcie/PCIe/
  s/phy/PHY/
  s/confgiruation/configuration/

No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
 2017-09-01 16:35:50 -05:00
Bharat Kumar Gogada
9cbbae2a62 PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space 
Updating device tree documentation with prefetchable memory
sapce.
Configuration space shifted to 64-bit address space.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
 2016-08-30 17:07:47 -05:00
Bharat Kumar Gogada
ab597d35ef PCI: xilinx-nwl: Add support for Xilinx NWL PCIe Host Controller 
Add PCIe Root Port driver for Xilinx PCIe NWL bridge IP.

[bhelgaas: wait for link like dw_pcie_wait_for_link(), simplify bitmap
error path, typos, whitespace, fold in Dan Carpenter's PTR_ERR() fix]
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
 2016-03-11 12:42:31 -06:00