2 Commits

Author	SHA1	Message	Date
Sergio Paracuellos	77945a345a	dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries ... MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' Hence update schema with the add of the entries related to clock. Since until now things were not properly being done we mark also 'clock' as required in the binding since this will be now the only way to properly retrieve frequency to be able to make a correct configuration of the PCIe phy registers. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210508070930.5290-3-sergio.paracuellos@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>	2021-05-14 16:16:28 +05:30
Sergio Paracuellos	27076a7358	dt-bindings: phy: Add binding for Mediatek MT7621 PCIe PHY ... Add bindings to describe Mediatek MT7621 PCIe PHY. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201121155037.21354-2-sergio.paracuellos@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>	2020-11-30 16:18:24 +05:30