7176 Commits

Author SHA1 Message Date
Grygorii Strashko
a323da4b43 arm64: dts: ti: k3-j7200-mcu: add mcu cpsw nuss node
Add DT node for The TI J7200 MCU SoC Gigabit Ethernet two ports Switch
subsystem (MCU CPSW NUSS).

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200923220938.30788-4-grygorii.strashko@ti.com
2020-09-24 05:55:11 -05:00
Grygorii Strashko
c5d73d8d49 arm64: dts: ti: k3-j7200-main: add main navss cpts node
Add DT node for Main NAVSS CPTS module.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200923220938.30788-3-grygorii.strashko@ti.com
2020-09-24 05:55:11 -05:00
Peter Ujfalusi
463742644e arm64: dts: ti: k3-j7200: add DMA support
Add the ringacc and udmap nodes for Main and MCU NAVSS.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200923220938.30788-2-grygorii.strashko@ti.com
2020-09-24 05:55:11 -05:00
Amit Kucheria
bac12f2569 arm64: dts: qcom: sm8250: Add thermal zones and throttling support
sm8250 has 24 thermal sensors split across two tsens controllers. Add
the thermal zones to expose them and wireup the cpus to throttle on
crossing passive temperature thresholds.

Signed-off-by: Amit Kucheria <amitk@kernel.org>
Link: https://lore.kernel.org/r/89b83b3caa4e32db08fe402cfa510feb25232aa0.1599732068.git.amitk@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-24 03:06:48 +00:00
Lokesh Vutla
26bd3f312c arm64: dts: ti: Add support for J7200 Common Processor Board
Add support for J7200 Common Processor Board.
The EVM architecture is very similar to J721E as follows:

+------------------------------------------------------+
|   +-------------------------------------------+      |
|   |                                           |      |
|   |        Add-on Card 1 Options              |      |
|   |                                           |      |
|   +-------------------------------------------+      |
|                                                      |
|                                                      |
|                     +-------------------+            |
|                     |                   |            |
|                     |   SOM             |            |
|  +--------------+   |                   |            |
|  |              |   |                   |            |
|  |  Add-on      |   +-------------------+            |
|  |  Card 2      |                                    |    Power Supply
|  |  Options     |                                    |    |
|  |              |                                    |    |
|  +--------------+                                    | <---
+------------------------------------------------------+
                                Common Processor Board

Common Processor board is the baseboard that has most of the actual
connectors, power supply etc. A SOM (System on Module) is plugged on
to the common processor board and this contains the SoC, PMIC, DDR and
basic high speed components necessary for functionality.

Note:
* The minimum configuration required to boot up the board is System On
  Module(SOM) + Common Processor Board.
* Since there is just a single SOM and Common Processor Board, we are
  maintaining common processor board as the base dts and SOM as the dtsi
  that we include. In the future as more SOM's appear, we should move
  common processor board as a dtsi and include configurations as dts.
* All daughter cards beyond the basic boards shall be maintained as
  overlays.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200914162231.2535-6-lokeshvutla@ti.com
2020-09-23 08:49:09 -05:00
Lokesh Vutla
d361ed8845 arm64: dts: ti: Add support for J7200 SoC
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded
products.

Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, two clusters of lockstep
  capable dual Cortex-R5F MCUs and a Centralized Device Management and
  Security Controller (DMSC).
* Configurable L3 Cache and IO-coherent architecture with high data
  throughput capable distributed DMA architecture under NAVSS.
* Integrated Ethernet switch supporting up to a total of 4 external ports
  in addition to legacy Ethernet switch of up to 2 ports.
* Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
  20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C
  and I2C, eCAP/eQEP, eHRPWM among other peripherals.
* One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
  management.

See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/20200914162231.2535-5-lokeshvutla@ti.com
2020-09-23 08:46:48 -05:00
Lokesh Vutla
21bb8c83c9 arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbs
To allow lesser dependency and better maintainability use CONFIG_ARCH_K3
for building dtbs for all K3 based devices. This is as per the
discussion in [0].

[0] https://lore.kernel.org/linux-arm-kernel/20200908112534.t5bgrjf7y3a6l2ss@akan/

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200914162231.2535-2-lokeshvutla@ti.com
2020-09-23 08:46:48 -05:00
Artem Lapkin
30a9a8c168 arm64: dts: rockchip: add ir-receiver node to rk3399-khadas-edge
add missed ir-receiver and ir_rx pinctl nodes to rk3399-khadas-edge
Khadas Edge board uses gpio-ir-receiver on RK_PB6 gpio

Signed-off-by: Artem Lapkin <art@khadas.com>
Link: https://lore.kernel.org/r/20200923130823.1612533-3-art@khadas.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-23 15:39:58 +02:00
Artem Lapkin
5d71f44569 arm64: dts: rockchip: add spiflash node to rk3399-khadas-edge
The Khadas Edge Boards uses winbond - w25q128 spi flash with 104Mhz

Signed-off-by: Artem Lapkin <art@khadas.com>
Link: https://lore.kernel.org/r/20200923130823.1612533-2-art@khadas.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-23 15:37:35 +02:00
Nobuhiro Iwamatsu
48dea9a700 arm64: dts: visconti: Add device tree for TMPV7708 RM main board
Add basic support for the Visconti TMPV7708 SoC peripherals -
  - CPU
    - CA53 x 4 and 2 cluster.
    - not support PSCI, currently only spin-table is supported.
  - Interrupt controller (ARM Generic Interrupt Controller)
  - Timer (ARM architected timer)
  - UART (ARM PL011 UART controller)
  - SPI (ARM PL022 SPI controller)
  - I2C (Synopsys DesignWare APB I2C Controller)
  - Pin control (Visconti specific)

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Reviewed-by: Punit Agrawal <punit1.agrawal@toshiba.co.jp>
2020-09-23 17:09:17 +09:00
David S. Miller
3ab0a7a0c3 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Two minor conflicts:

1) net/ipv4/route.c, adding a new local variable while
   moving another local variable and removing it's
   initial assignment.

2) drivers/net/dsa/microchip/ksz9477.c, overlapping changes.
   One pretty prints the port mode differently, whilst another
   changes the driver to try and obtain the port mode from
   the port node rather than the switch node.

Signed-off-by: David S. Miller <davem@davemloft.net>
2020-09-22 16:45:34 -07:00
David Bauer
f1ec83f880 arm64: dts: rockchip: Add support for FriendlyARM NanoPi R2S
This adds support for the NanoPi R2S from FriendlyARM.

Rockchip RK3328 SoC
1GB DDR4 RAM
Gigabit Ethernet (WAN)
Gigabit Ethernet (USB3) (LAN)
USB 2.0 Host Port
MicroSD slot
Reset button
WAN - LAN - SYS LED

Signed-off-by: David Bauer <mail@david-bauer.net>
Link: https://lore.kernel.org/r/20200920154528.88185-2-mail@david-bauer.net
[adapted from sdmmc0m1_gpio to renamed sdmmc0m1_pin]
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-22 16:03:19 +02:00
Kishon Vijay Abraham I
66db854b1f arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances
J721E Common Processor Board has PCIe connectors for the 1st three PCIe
instances. Configure the three PCIe instances in RC mode and disable the
4th PCIe instance.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20200914152115.1788-3-kishon@ti.com
2020-09-22 08:19:47 -05:00
Kishon Vijay Abraham I
4e5833884f arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes
Add PCIe device tree nodes (both RC and EP) for the four
PCIe instances here.

Also add the missing translations required in the "ranges"
DT property of cbass_main to access all the four PCIe
instances.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20200914152115.1788-2-kishon@ti.com
2020-09-22 08:19:47 -05:00
Krzysztof Kozlowski
912a6e2ef6 arm64: dts: imx8mq-librem5: correct GPIO hog property
Correct the name of property for GPIO specifier in GPIO hog.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Krzysztof Kozlowski
ac938aa9ae arm64: dts: imx8mm-var-som-symphony: Drop wake-up source from RTC
The RTC on Symphony board does not have its interrupt pin connected to
the SoC, therefore it is not capable of waking up.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Krzysztof Kozlowski
d8fa4792da arm64: dts: imx8mq: correct interrupt flags
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW  = 1 = IRQ_TYPE_EDGE_RISING

Correct the interrupt flags, assuming the author of the code wanted same
logical behavior behind the name "ACTIVE_xxx", this is:
  ACTIVE_LOW  => IRQ_TYPE_LEVEL_LOW

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Krzysztof Kozlowski
4153f7811a arm64: dts: imx8mn: correct interrupt flags
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW  = 1 = IRQ_TYPE_EDGE_RISING

Correct the interrupt flags, assuming the author of the code wanted same
logical behavior behind the name "ACTIVE_xxx", this is:
  ACTIVE_LOW  => IRQ_TYPE_LEVEL_LOW

For level low interrupts, enable also internal pull up.  It is
required at least on imx8mm-evk, according to schematics.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Krzysztof Kozlowski
5f67317bd9 arm64: dts: imx8mm: correct interrupt flags
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW  = 1 = IRQ_TYPE_EDGE_RISING

Correct the interrupt flags, assuming the author of the code wanted same
logical behavior behind the name "ACTIVE_xxx", this is:
  ACTIVE_LOW  => IRQ_TYPE_LEVEL_LOW
  ACTIVE_HIGH => IRQ_TYPE_LEVEL_HIGH

In case of level low interrupts, enable also internal pull up.  It is
required at least on imx8mm-evk, according to schematics.

The schematics for Variscite imx8mm-var-som are not available and
I was unable to get proper configuration from Variscite.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Krzysztof Kozlowski
1d93b292af arm64: dts: imx8mm-var-som-symphony: fix ptn5150 interrupts
Conversion of int-gpios into interrupts property requires also
interrupt-parent and uses different flags.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Zhao Qiang
f3cbcbbb4b arm64: dts: layerscape: correct watchdog clocks for LS1088A
On LS1088A, watchdog clk are divided by 16, correct it in dts.

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Michael Walle
499b767875 arm64: dts: freescale: sl28: enable fan support
Add a pwm-fan mapped to the PWM channel 0 which is connected to the
fan connector of the carrier.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Michael Walle
3672d6fa6e arm64: dts: freescale: sl28: enable LED support
Now that we have support for GPIO lines of the SMARC connector, enable
LED support on the KBox A-230-LS. There are two LEDs without fixed
functions, one is yellow and one is green. Unfortunately, it is just one
multi-color LED, thus while it is possible to enable both at the same
time it is hard to tell the difference between "yellow only" and "yellow
and green".

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Michael Walle
945710bbdb arm64: dts: freescale: sl28: map GPIOs to input events
Now that we have support for GPIO lines of the SMARC connector, map the
sleep, power and lid switch signals to the corresponding keys using the
gpio-keys and gpio-keys-polled drivers. The power and sleep signals have
dedicated interrupts, thus we use these ones. The lid switch is just
mapped to a GPIO input and needs polling.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Michael Walle
c86e4202fd arm64: dts: freescale: sl28: enable sl28cpld
Add the board management controller node.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Fabio Estevam
d367e7d335 arm64: dts: imx8mq-evk: Add MIPI DSI support
imx8mq-evk has a MIPI DSI port that can be used to connect a Raydium
RM67191 panel.

Add support for it.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Wasim Khan
f7d48ffcfc arm64: dts: layerscape: Add label to pcie nodes
Add label to pcie nodes so that they are easy to
refer.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Krzysztof Kozlowski
7358e05bdd arm64: dts: imx8mn-var-som-symphony: Add Variscite Symphony board with VAR-SOM-MX8MN
Add a basic DTS for Variscite Symphony evaluation kit with VAR-SOM-MX8MN
(i.MX 8M Nano) System on Module.  This brings up the board with basic
functionalities although still few issues remain (e.g. I2C3 and USB OTG
port, although it might not be the problem of DTS).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Krzysztof Kozlowski
ade0176dd8 arm64: dts: imx8mn-var-som: Add Variscite VAR-SOM-MX8MN System on Module
Add DTSI of Variscite VAR-SOM-MX8MN (Nano) System on Module in a basic
version, delivered with Variscite Symphony Evaluation kit.  This version
comes with:
- 1 GB of RAM,
- 16 GB eMMC,
- Gigabit Ethernet PHY,
- 802.11 ac/a/b/g/n WiFi with 4.2 Bluetooth,
- CAN bus,
- Audio codec (not yet configured in DTSI).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 17:06:04 +08:00
Amit Singh Tomar
13441281bd arm64: dts: actions: Add DMA Controller for S700
This commit adds DMA controller present on Actions S700, it differs from
S900 in terms of number of dma channels and requests.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-09-22 12:41:36 +05:30
Amit Singh Tomar
4bb1eb3cd4 arm64: dts: actions: limit address range for pinctrl node
After commit 7cdf8446ed1d ("arm64: dts: actions: Add pinctrl node for
Actions Semi S700") following error has been observed while booting
Linux on Cubieboard7-lite(based on S700 SoC).

[    0.257415] pinctrl-s700 e01b0000.pinctrl: can't request region for
resource [mem 0xe01b0000-0xe01b0fff]
[    0.266902] pinctrl-s700: probe of e01b0000.pinctrl failed with error -16

This is due to the fact that memory range for "sps" power domain controller
clashes with pinctrl.

One way to fix it, is to limit pinctrl address range which is safe
to do as current pinctrl driver uses address range only up to 0x100.

This commit limits the pinctrl address range to 0x100 so that it doesn't
conflict with sps range.

Fixes: 7cdf8446ed1d ("arm64: dts: actions: Add pinctrl node for Actions
Semi S700")

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Suggested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-09-22 12:41:27 +05:30
Krzysztof Kozlowski
c48cf8e5d8 arm64: dts: imx8mn-ddr4-evk: Remove unneeded PMIC pin configuration
The pin configuration for PMIC interrupt is already set by
imx8mn-evk.dtsi with exactly the same values.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 09:47:37 +08:00
Krzysztof Kozlowski
12cdf9d2c9 arm64: dts: imx8mm-var-som-symphony: Adjust ethernet pin configuration
The Symphony board uses GPIO from expander as Ethernet PHY reset pin,
not the GPIO1_IO9.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 09:47:35 +08:00
Krzysztof Kozlowski
510ed6749f arm64: dts: imx8mm-var-som-symphony: Remove unneeded i2c3 properties
The i2c3 clock frequency and pin configuration are already set by
imx8mm-var-som.dtsi.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22 09:47:23 +08:00
Crystal Guo
f866c47154 arm64: dts: mt8183: update watchdog device node
The watchdog driver for MT8183 relies on DT data, so the fallback
compatible MT6589 won't work, need to update watchdog device node
to sync with watchdog dt-binding document.

Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-21 18:57:33 +02:00
Roger Quadros
c65176fd49 arm64: dts: ti: k3-j721e: Rename mux header and update macro names
We intend to use one header file for SERDES MUX for all
TI SoCs so rename the header file.

The exsting macros are too generic. Prefix them with SoC name.

While at that, add the missing configurations for completeness.

Fixes: b766e3b0d5f6 ("arm64: dts: ti: k3-j721e-main: Add system controller node and SERDES lane mux")
Reported-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20200918165930.2031-1-rogerq@ti.com
2020-09-21 07:17:20 -05:00
Hsin-Yi Wang
1276be23fd arm64: dts: mt8173: elm: Fix nor_flash node property
bus-width and non-removable is not used by the driver.
max-frequency should be spi-max-frequency for flash node.

Fixes: 689b937bedde ("arm64: dts: mediatek: add mt8173 elm and hana board")
Reported-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20200727074124.3779237-1-hsinyi@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-21 12:05:30 +02:00
Krzysztof Kozlowski
e2a8fa1e0f arm64: dts: mediatek: fix tca6416 reset GPIOs in pumpkin
Correct the property for reset GPIOs of tca6416 GPIO expander.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200910175733.11046-4-krzk@kernel.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-21 11:45:32 +02:00
Krzysztof Kozlowski
fa7a98eb47 arm64: dts: zynqmp-zcu100-revC: correct interrupt flags
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW  = 1 = IRQ_TYPE_EDGE_RISING

Correct the interrupt flags, assuming the author of the code wanted same
logical behavior behind the name "ACTIVE_xxx", this is:
  ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

Link: https://lore.kernel.org/r/20200917185052.5084-1-krzk@kernel.org
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-21 10:06:16 +02:00
Jerome Brunet
63fafc5a04 arm64: dts: meson: initial support for aml-s905x-cc v2
Add initial support for the libretech aml-s905x-cc (Le Potato) v2

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200915141921.57258-3-jbrunet@baylibre.com
2020-09-18 13:35:27 -07:00
Christian Hewitt
98d24896ee arm64: dts: meson: add support for the ODROID-N2+
HardKernel ODROID-N2+ uses an Amlogic S922X rev. C chip capable of higher
clock speeds than the original ODROID-N2.

The rev. C support a slighly higher VDDCPU_A & VDDCPU_B voltages and supports
the same OPPs as the Amlogic A311D SoC from the same G12B family.

Suggested-by: Dongjin Kim <tobetter@hardkernel.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20200915152432.30616-4-narmstrong@baylibre.com
2020-09-18 13:32:45 -07:00
Christian Hewitt
ef599f5f3e arm64: dts: meson: convert ODROID-N2 to dtsi
Convert the current ODROID-N2 dts into a common dtsi in preparation
for adding ODROID-N2+ support.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20200915152432.30616-2-narmstrong@baylibre.com
2020-09-18 13:32:44 -07:00
Thierry Reding
639448912b arm64: tegra: Initial Tegra234 VDK support
The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It
supports a subset of the peripherals that will be available in the final
chip and serves as a bootstrapping platform.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18 15:58:07 +02:00
Geert Uytterhoeven
c91dfc9818 arm64: dts: renesas: r8a774c0: Fix MSIOF1 DMA channels
According to Technical Update TN-RCT-S0352A/E, MSIOF1 DMA can only be
used with SYS-DMAC0 on R-Car E3.

Fixes: 62c0056f1c3eb15d ("arm64: dts: renesas: r8a774c0: Add MSIOF nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200917132117.8515-3-geert+renesas@glider.be
2020-09-18 09:10:58 +02:00
Geert Uytterhoeven
453802c463 arm64: dts: renesas: r8a77990: Fix MSIOF1 DMA channels
According to Technical Update TN-RCT-S0352A/E, MSIOF1 DMA can only be
used with SYS-DMAC0 on R-Car E3.

Fixes: 8517042060b55a37 ("arm64: dts: renesas: r8a77990: Add DMA properties to MSIOF nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200917132117.8515-2-geert+renesas@glider.be
2020-09-18 09:10:58 +02:00
Samuel Holland
db9c6ad2e8
arm64: dts: allwinner: a64: Update the audio codec compatible
The audio codec in the A64 has some differences from the A33 codec, so
it needs its own compatible. Since the two codecs are similar, the A33
codec compatible is kept as a fallback.

Using the correct compatible fixes a channel inversion issue and cleans
up some DAPM widgets that are no longer used.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200726012557.38282-8-samuel@sholland.org
2020-09-17 18:37:32 +02:00
Samuel Holland
631e6a3530
arm64: dts: allwinner: a64: Update codec widget names
The sun8i-codec driver introduced a new set of DAPM widgets that more
accurately describe the hardware topology. Update the various device
trees to use the new widget names.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200726012557.38282-7-samuel@sholland.org
2020-09-17 18:37:31 +02:00
Jon Hunter
2b9ee384b4 arm64: tegra: Populate EEPROMs for Jetson Xavier NX
Populate the EEPROMs that are present on the Jetson Xavier NX developer
platform.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-17 17:45:42 +02:00
Jon Hunter
a4387f2973 arm64: tegra: Add label properties for EEPROMs
Populate the label property for the AT24 EEPROMs on the various Jetson
platforms. Note that the name 'module' is used to identify the EEPROM
on the processor module board and the name 'system' is used to identify
the EEPROM on the main base board (which is sometimes referred to as
the carrier board).

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-17 17:45:28 +02:00
Bjorn Andersson
02ae4a0ed1 arm64: dts: qcom: sm8250: Add cpufreq hw node
Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores
on SM8250 SoCs.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Amit Kucheria <amitk@kernel.org>
Link: https://lore.kernel.org/r/20200915072423.18437-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-17 03:57:12 +00:00