2 Commits

Author	SHA1	Message	Date
Grygorii Strashko	74e29703a7	dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e soc ... TI AM654x/J721E SoCs have the same PHY interface selection mechanism for CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields placement is different. This patch adds corresponding compatible strings to enable support for TI AM654x/J721E SoCs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>	2020-03-20 19:34:29 +05:30
Grygorii Strashko	5b9bf512ca	dt-bindings: phy: add cpsw port interface mode selection phy bindings ... Add CPSW Port's Interface Mode Selection PHY (phy-gmii-sel) DT Bindings Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>	2018-12-12 10:01:40 +05:30