4 Commits

Author	SHA1	Message	Date
Georgi Djakov	d4f76de374	clk: qcom: Add support for SR2 PLLs ... Add support for SR2 type pll operations. SR2 is optimized for Time Interval Error (TIE) or absolute jitter. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2015-07-07 17:19:58 -07:00
Stephen Boyd	ae3669ac5c	clk: qcom: Add support for setting rates on PLLs ... Some PLLs may require changing their rate at runtime. Add support for these PLLs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2014-09-22 15:16:53 -07:00
Stephen Boyd	d8c25d3a1a	clk: qcom: pll: Add support for configuring SR PLLs ... Some SR type PLLs need to be configured for a certain rate when linux boots. Add support for these types of PLLs so that we can program PLL15's rate on apq8064. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2014-07-15 16:39:02 -07:00
Stephen Boyd	9e2631313c	clk: qcom: Add support for phase locked loops (PLLs) ... Add support for Qualcomm's PLLs (phase locked loops). This is sufficient enough to be able to determine the rate the PLL is running at. We can add rate setting support later when it's needed. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>	2014-01-16 12:00:59 -08:00