4 Commits

Author	SHA1	Message	Date
Andrew Lunn	4b8f7a11c9	ARM: MM: Add DT binding for Feroceon L2 cache ... Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>	2014-02-22 20:43:49 +00:00
Chao Xie	c2b7e05c75	ARM: cache: add dt support for tauros2 cache ... Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>	2012-08-16 16:16:50 +08:00
Andrew Lunn	278b45b06b	ARM: Orion: DT support for IRQ and GPIO Controllers ... Both IRQ and GPIO controllers can now be represented in DT. The IRQ controllers are setup first, and then the GPIO controllers. Interrupts for GPIO lines are placed directly after the main interrupts in the interrupt space. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@googlemail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Josh Coombs <josh.coombs@gmail.com> Tested-by: Simon Baatz <gmbnomis@gmail.com>	2012-07-27 16:48:14 +02:00
Haojian Zhuang	ace1297f72	Documentation: update docs for mmp dt ... Append interrupt controller and timer document for mmp. Updates documents for gpio and i2c. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de>	2012-05-05 16:40:08 +08:00