7 Commits

Author SHA1 Message Date
Tiezhu Yang
cbab54d9c2 MIPS: No need to check CPU 0 in {loongson3,bmips,octeon}_cpu_disable()
After commit 9cce844abf07 ("MIPS: CPU#0 is not hotpluggable"),
c->hotpluggable is 0 for CPU 0 and it will not generate a control
file in sysfs for this CPU:

[root@linux loongson]# cat /sys/devices/system/cpu/cpu0/online
cat: /sys/devices/system/cpu/cpu0/online: No such file or directory
[root@linux loongson]# echo 0 > /sys/devices/system/cpu/cpu0/online
bash: /sys/devices/system/cpu/cpu0/online: Permission denied

So no need to check CPU 0 in {loongson3,bmips,octeon}_cpu_disable(),
just remove them.

Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-27 10:38:12 +01:00
Tiezhu Yang
381ad3843b MIPS: Loongson64: SMP: Fix up play_dead jump indicator
In play_dead function, the whole 64-bit PC mailbox was used as a indicator
to determine if the master core had written boot jump information.

However, after we introduced CSR mailsend, the hardware will not guarante
an atomic write for the 64-bit PC mailbox. Thus we have to use the lower
32-bit which is written at the last as the jump indicator instead.

Signed-off-by: Lu Zeng <zenglu@loongson.cn>
Signed-off-by: Jun Yi <yijun@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-11 23:53:13 +01:00
Tiezhu Yang
fed4955f30 MIPS: Loongson64: Add Mail_Send support for 3A4000+ CPU
Loongson 3A4000+ CPU has per-core Mail_Send register to send mail,
there is no need to maintain register address of each core and node,
just simply specify cpu number.

Signed-off-by: Lu Zeng <zenglu@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-11 23:52:50 +01:00
Tiezhu Yang
42831cd708 MIPS: Loongson64: Set IPI_Enable register per core by itself
In the current code, for example, core 1 sets Core[0, 1, 2, 3]_IPI_Enalbe
register and core 2, 3 do the same thing on the 1-way Loongson64 platform,
this is not necessary. Set IPI_Enable register per core by itself to avoid
duplicate operations and make the logic more clear.

Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-11-11 23:52:26 +01:00
Arnd Bergmann
c02e963044 mips: loongsoon2ef: remove private clk api
As platforms are moving to COMMON_CLK in general, loongson2ef
stuck out as something that has a private implementation but
does not actually use it except for setting the frequency of
the CPU itself from the loongson2_cpufreq driver.

Change that driver to call the register setting function directly
and remove the rest of the stub implementation.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-04-16 17:34:23 +02:00
Jiaxun Yang
8bec3875c5 MIPS: Loongson64: Drop legacy IRQ code
We've made generic irqchip drivers for Loongson-3 platform, it's time
to say goodbye to these legacy code.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Co-developed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-03-25 16:07:11 +01:00
Jiaxun Yang
6fbde6b492
MIPS: Loongson64: Move files to the top-level directory
Current Loongson-3 code can share among all Loongson64 processors.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Paul Burton <paulburton@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: chenhc@lemote.com
Cc: paul.burton@mips.com
2019-11-01 14:31:28 -07:00