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4 Commits

Author SHA1 Message Date
Dinh Nguyen
80c6b7a089 clk: socfpga: agilex: add clock driver for the Agilex platform 
For the most part the Agilex clock structure is very similar to
Stratix10, so we re-use most of the Stratix10 clock driver.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20200512181647.5071-5-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-05-26 19:13:05 -07:00
Dinh Nguyen
762d961aee clk: socfpga: stratix10: use new parent data scheme 
Convert, where possible, the stratix10 clock driver to the new parent
data scheme by specifying the parent data for clocks that have multiple
parents.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20200512181647.5071-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-05-26 19:13:05 -07:00
Dinh Nguyen
8c0e783d2c clk: socfpga: stratix10: simplify parameter passing 
Just pass the clock pointer structure to the various register functions.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20200114160726.19771-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2020-02-12 15:42:04 -08:00
Dinh Nguyen
07afb8db73 clk: socfpga: stratix10: add clock driver for Stratix10 platform 
Add a clock driver for the Stratix10 SoC. The driver is similar to the
Cyclone5/Arria10 platforms, with the exception that this driver only uses
one single clock binding.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2018-04-06 10:12:35 -07:00