4718 Commits

Author SHA1 Message Date
Linus Torvalds
bbfe0d6b8b This is the bulk of changes in the GPIO subsystem for the
v5.4 kernel cycle.
 
 Core changes:
 
 - Support hierarchical GPIO irqchips. We now have three
   consumers that can use this: Intel IXP4xx, ThunderX and
   Qualcomm SPMI GPIO (in the pinctrl subsystem). The support
   code has been long in the making and hashed out so it should
   be easily adaptable for all hierarchical irqchip parents.
   The code only gets compiled in if hierarchical irqchip
   is used at the topmost irq controller at least, as the
   hierarchical irqchip requires strict hierarchy all the
   way up in the system.
 
 - Determine the need for a "valid_mask" for GPIO lines on the
   gpio_chip and conversely for the "valid_mask" for the GPIO
   interrupt chip interrupt lines by looking for a
   .init_valid_mask() callback in the main chip or GPIO interrupt
   chip respectively. Allocate it with bitmap_alloc().
 
 - Isolate the device tree/open firmware GPIO description code
   out in its own file properly.
 
 - Isolate the ACPI GPIO description code out in its own file
   properly.
 
 - Drop a whole lot of #ifdef:s in the main includes: it does
   not hurt to keep the include items around, and we get
   quicker and clearer compile failures if the appropriate
   kernel symbols are not selected for drivers.
 
 New/deleted drivers:
 
 - New driver for Aspeed SGPIO.
 
 - The KS8695 driver is deleted as the platform gets deleted
   from arch/arm in this kernel cycle.
 
 - The Cirrus Logic Madera driver now supports CS47L92 and
   CS47L15.
 
 - The Freescale MPC8xxx now supports LS1028A and LS1088A.
 
 Driver improvements:
 
 - We pass the GPIO irqchip intialization by directly filling
   in the struct instead of using set-up functions (the new
   way) for Intel MID, Lynxpoint, Merrifield, XLP, HLWD, Aspeed,
   ZX, VF610, TQMX86, MT7621, Zynq and EP93xx.
 
 Out-of-band changes:
 
 - Fix a GPIO header inclusion in Unicore - no response from
   maintainer.
 
 - Drop FMC subsystem from MAINTAINERS - was deleted in the
   GPIO tree last cycle so let's mop up the shards.
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Merge tag 'gpio-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO updates from Linus Walleij:
 "This is the bulk of changes in the GPIO subsystem for the v5.4 kernel
  cycle.

  Core changes:

   - Support hierarchical GPIO irqchips.

     We now have three consumers that can use this: Intel IXP4xx,
     ThunderX and Qualcomm SPMI GPIO (in the pinctrl subsystem).

     The support code has been long in the making and hashed out so it
     should be easily adaptable for all hierarchical irqchip parents.
     The code only gets compiled in if hierarchical irqchip is used at
     the topmost irq controller at least, as the hierarchical irqchip
     requires strict hierarchy all the way up in the system.

   - Determine the need for a "valid_mask" for GPIO lines on the
     gpio_chip and conversely for the "valid_mask" for the GPIO
     interrupt chip interrupt lines by looking for a .init_valid_mask()
     callback in the main chip or GPIO interrupt chip respectively.
     Allocate it with bitmap_alloc().

   - Isolate the device tree/open firmware GPIO description code out in
     its own file properly.

   - Isolate the ACPI GPIO description code out in its own file
     properly.

   - Drop a whole lot of #ifdef:s in the main includes: it does not hurt
     to keep the include items around, and we get quicker and clearer
     compile failures if the appropriate kernel symbols are not selected
     for drivers.

  New/deleted drivers:

   - New driver for Aspeed SGPIO.

   - The KS8695 driver is deleted as the platform gets deleted from
     arch/arm in this kernel cycle.

   - The Cirrus Logic Madera driver now supports CS47L92 and CS47L15.

   - The Freescale MPC8xxx now supports LS1028A and LS1088A.

  Driver improvements:

   - We pass the GPIO irqchip intialization by directly filling in the
     struct instead of using set-up functions (the new way) for Intel
     MID, Lynxpoint, Merrifield, XLP, HLWD, Aspeed, ZX, VF610, TQMX86,
     MT7621, Zynq and EP93xx.

  Out-of-band changes:

   - Fix a GPIO header inclusion in Unicore - no response from
     maintainer.

   - Drop FMC subsystem from MAINTAINERS - was deleted in the GPIO tree
     last cycle so let's mop up the shards"

* tag 'gpio-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (82 commits)
  gpiolib: of: add a fallback for wlf,reset GPIO name
  gpio: htc-egpio: Remove unused exported htc_egpio_get_wakeup_irq()
  gpio: remove explicit comparison with 0
  gpio: creg-snps: use devm_platform_ioremap_resource() to simplify code
  gpio: devres: Switch to EXPORT_SYMBOL_GPL()
  gpio: of: Switch to EXPORT_SYMBOL_GPL()
  gpio: of: Make of_gpio_simple_xlate() private
  gpio: of: Make of_get_named_gpiod_flags() private
  gpio: aspeed: Add in ast2600 details to Aspeed driver
  gpio: aspeed: Use ngpio property from device tree if available
  gpio: aspeed: Setup irqchip dynamically
  gpio/aspeed: Fix incorrect number of banks
  gpio: aspeed: Update documentation with ast2600 controllers
  gpio: Initialize the irqchip valid_mask with a callback
  gpiolib: acpi: make acpi_can_fallback_to_crs() static
  gpio: Fix further merge errors
  gpio: Fix up merge collision in include file
  gpio: of: Normalize return code variable name
  gpio: gpiolib: Normalize return code variable name
  gpio: ep93xx: Pass irqchip when adding gpiochip
  ...
2019-09-16 14:06:50 -07:00
Dmitry Torokhov
11c43bb022 gpiolib: of: add a fallback for wlf,reset GPIO name
The old Arizona binding did not use -gpio or -gpios suffix, so
devm_gpiod_get() does not work for it. As it is the one of a few users
of devm_gpiod_get_from_of_node() API that I want to remove, I'd rather
have a small quirk in the gpiolib OF handler, and switch Arizona
driver to devm_gpiod_get().

Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Link: https://lore.kernel.org/r/20190911075215.78047-2-dmitry.torokhov@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-12 10:29:17 +01:00
Geert Uytterhoeven
c34a024e4e gpio: htc-egpio: Remove unused exported htc_egpio_get_wakeup_irq()
This function was never used upstream, and is a relic of the original
handhelds.org code the htc-egpio driver was based on.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190910141529.21030-1-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-12 10:07:44 +01:00
Saiyam Doshi
2efc6bfadb gpio: remove explicit comparison with 0
No need to compare return value with 0. In case of non-zero
return value, the if condition will be true.

This makes intent a bit more clear to the reader.
"if (x) then", compared to "if (x is not zero) then".

Signed-off-by: Saiyam Doshi <saiyamdoshi.in@gmail.com>
Link: https://lore.kernel.org/r/20190907173910.GA9547@SD
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-12 00:05:29 +01:00
YueHaibing
aba30f6f31 gpio: creg-snps: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20190906131032.22148-1-yuehaibing@huawei.com
Acked-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11 14:50:02 +01:00
Geert Uytterhoeven
ac57199180 gpio: devres: Switch to EXPORT_SYMBOL_GPL()
Change all exported symbols for managed GPIO functions from
EXPORT_SYMBOL() to EXPORT_SYMBOL_GPL(), like is used for their
non-managed counterparts.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190906084539.21838-5-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11 14:47:39 +01:00
Geert Uytterhoeven
6d6624554d gpio: of: Switch to EXPORT_SYMBOL_GPL()
All exported functions provide genuine Linux-specific functionality.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190906084539.21838-4-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11 14:46:52 +01:00
Geert Uytterhoeven
b0c7e73b51 gpio: of: Make of_gpio_simple_xlate() private
Since commit 9a95e8d25a140ba9 ("gpio: remove etraxfs driver"), there are
no more users of of_gpio_simple_xlate() outside gpiolib-of.c.
All GPIO drivers that need it now rely on of_gpiochip_add() setting it
up as the default translate function.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190906084539.21838-3-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11 14:46:02 +01:00
Geert Uytterhoeven
c83d3c7733 gpio: of: Make of_get_named_gpiod_flags() private
Since commit f626d6dfb7098525 ("gpio: of: Break out OF-only code"),
there are no more users of of_get_named_gpiod_flags() outside
gpiolib-of.c.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190906084539.21838-2-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11 14:45:01 +01:00
Rashmica Gupta
ab4a85534c gpio: aspeed: Add in ast2600 details to Aspeed driver
The ast2600 is a new generation of SoC from ASPEED. Similarly to the
ast2400 and ast2500, it has a GPIO controller for it's 3.3V GPIO pins.
Additionally, it has a GPIO controller for 1.8V GPIO pins.

As the register names for both controllers are the same and the 36 1.8V
GPIOs and the first 36 of the 3.3V GPIOs are all bidirectional, we can
use the same configuration struct and use the ngpio property to
differentiate between the two sets of GPIOs.

Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
Link: https://lore.kernel.org/r/20190906063737.15428-1-rashmica.g@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11 11:13:11 +01:00
Rashmica Gupta
be2a7e2d5d gpio: aspeed: Use ngpio property from device tree if available
Use the ngpio property from the device tree if it exists. If it doesn't
then fallback to the hardcoded value in the config.

This is in preparation for adding ast2600 support. The ast2600 SoC has
two GPIO controllers and so requires two instances of the GPIO driver.
We use the ngpio property to different between them as they have
different numbers of GPIOs.

Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
Link: https://lore.kernel.org/r/20190906062727.13521-1-rashmica.g@gmail.com
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11 11:11:16 +01:00
Rashmica Gupta
3d64a5a742 gpio: aspeed: Setup irqchip dynamically
This is in preparation for adding ast2600 support. The ast2600 SoC
requires two instances of the GPIO driver as it has two GPIO
controllers. Each instance needs it's own irqchip.

Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
Link: https://lore.kernel.org/r/20190906062644.13445-1-rashmica.g@gmail.com
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11 11:08:59 +01:00
Rashmica Gupta
3c4710ae6f gpio/aspeed: Fix incorrect number of banks
The current calculation for the number of GPIO banks is only correct if
the number of GPIOs is a multiple of 32 (if there were 31 GPIOs we would
currently say there are 0 banks, which is incorrect).

Fixes: 361b79119a4b7 ('gpio: Add Aspeed driver')

Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190906062623.13354-1-rashmica.g@gmail.com
Reviewed-by: Joel Stanley <joel@jms.d.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11 11:04:55 +01:00
Hans de Goede
61f7f7c8f9 gpiolib: acpi: Add gpiolib_acpi_run_edge_events_on_boot option and blacklist
Another day; another DSDT bug we need to workaround...

Since commit ca876c7483b6 ("gpiolib-acpi: make sure we trigger edge events
at least once on boot") we call _AEI edge handlers at boot.

In some rare cases this causes problems. One example of this is the Minix
Neo Z83-4 mini PC, this device has a clear DSDT bug where it has some copy
and pasted code for dealing with Micro USB-B connector host/device role
switching, while the mini PC does not even have a micro-USB connector.
This code, which should not be there, messes with the DDC data pin from
the HDMI connector (switching it to GPIO mode) breaking HDMI support.

To avoid problems like this, this commit adds a new
gpiolib_acpi.run_edge_events_on_boot kernel commandline option, which
allows disabling the running of _AEI edge event handlers at boot.

The default value is -1/auto which uses a DMI based blacklist, the initial
version of this blacklist contains the Neo Z83-4 fixing the HDMI breakage.

Cc: stable@vger.kernel.org
Cc: Daniel Drake <drake@endlessm.com>
Cc: Ian W MORRISON <ianwmorrison@gmail.com>
Reported-by: Ian W MORRISON <ianwmorrison@gmail.com>
Suggested-by: Ian W MORRISON <ianwmorrison@gmail.com>
Fixes: ca876c7483b6 ("gpiolib-acpi: make sure we trigger edge events at least once on boot")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20190827202835.213456-1-hdegoede@redhat.com
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Ian W MORRISON <ianwmorrison@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11 10:46:54 +01:00
Linus Walleij
5fbe5b5883 gpio: Initialize the irqchip valid_mask with a callback
After changing the valid_mask for the struct gpio_chip
to detect the need and presence of a valid mask with the
presence of a .init_valid_mask() callback to fill it in,
we augment the gpio_irq_chip to use the same logic.

Switch all driver using the gpio_irq_chio valid_mask
over to this new method.

This makes sure the valid_mask for the gpio_irq_chip gets
filled in when we add the gpio_chip, which makes it a
little easier to switch over drivers using the old
way of setting up gpio_irq_chip over to the new method
of passing the gpio_irq_chip along with the gpio_chip.
(See drivers/gpio/TODO for details.)

Cc: Joel Stanley <joel@jms.id.au>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Link: https://lore.kernel.org/r/20190904140104.32426-1-linus.walleij@linaro.org
2019-09-11 01:09:37 +01:00
Dmitry Torokhov
4f78d91c72 gpiolib: acpi: make acpi_can_fallback_to_crs() static
It is not used outside gpiolib-acpi.c module, so there is no need to
export it.

Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Link: https://lore.kernel.org/r/20190904172624.GA76617@dtor-ws
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-10 11:34:20 +01:00
Dmitry Torokhov
1dea33e84d gpiolib: of: fix fallback quirks handling
We should only try to execute fallback quirks handling when previous
call returned -ENOENT, and not when we did not get -EPROBE_DEFER.
The other errors should be treated as hard errors: we did find the GPIO
description, but for some reason we failed to handle it properly.

The fallbacks should only be executed when previous handlers returned
-ENOENT, which means the mapping/description was not found.

Also let's remove the explicit deferral handling when iterating through
GPIO suffixes: it is not needed anymore as we will not be calling
fallbacks for anything but -ENOENT.

Fixes: df451f83e1fc ("gpio: of: fix Freescale SPI CS quirk handling")
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Link: https://lore.kernel.org/r/20190903231856.GA165165@dtor-ws
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-10 11:31:35 +01:00
Linus Walleij
6babaaeb1f intel-gpio for v5.4-1
The clean up of IRQ chip initialization has been done in few drivers.
 Stale record in MAINTAINERS database is removed.
 
 The following is an automated git shortlog grouped by driver:
 
 intel-mid:
  -  Pass irqchip when adding gpiochip
  -  MAINTAINERS: Remove stale record for gpio-intel-mid.c
 
 lynxpoint:
  -  Pass irqchip when adding gpiochip
 
 merrifield:
  -  Pass irqchip when adding gpiochip
 
 pch:
  -  Use dev_get_drvdata
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Merge tag 'intel-gpio-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel into devel

intel-gpio for v5.4-1

The clean up of IRQ chip initialization has been done in few drivers.
Stale record in MAINTAINERS database is removed.

The following is an automated git shortlog grouped by driver:

intel-mid:
 -  Pass irqchip when adding gpiochip
 -  MAINTAINERS: Remove stale record for gpio-intel-mid.c

lynxpoint:
 -  Pass irqchip when adding gpiochip

merrifield:
 -  Pass irqchip when adding gpiochip

pch:
 -  Use dev_get_drvdata
2019-09-10 11:10:01 +01:00
Kent Gibson
5ca2f54b59 gpio: fix line flag validation in lineevent_create
lineevent_create should not allow any of GPIOHANDLE_REQUEST_OUTPUT,
GPIOHANDLE_REQUEST_OPEN_DRAIN or GPIOHANDLE_REQUEST_OPEN_SOURCE to be set.

Fixes: d7c51b47ac11 ("gpio: userspace ABI for reading/writing GPIO lines")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Kent Gibson <warthog618@gmail.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-09-09 10:04:53 +02:00
Kent Gibson
e95fbc130a gpio: fix line flag validation in linehandle_create
linehandle_create should not allow both GPIOHANDLE_REQUEST_INPUT
and GPIOHANDLE_REQUEST_OUTPUT to be set.

Fixes: d7c51b47ac11 ("gpio: userspace ABI for reading/writing GPIO lines")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Kent Gibson <warthog618@gmail.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-09-09 10:01:55 +02:00
Wei Yongjun
59929d3a2e gpio: mockup: add missing single_release()
When using single_open() for opening, single_release() should be
used instead of seq_release(), otherwise there is a memory leak.

Fixes: 2a9e27408e12 ("gpio: mockup: rework debugfs interface")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-09-09 09:55:27 +02:00
Linus Walleij
fbdf8d4bef gpio: Fix further merge errors
The previous merge of v5.3-rc7 was struggle enough, now it
gave rise to new errors and now I fix those too.

Fixes: 151a41014bff ("Merge tag 'v5.3-rc7' into devel")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-06 12:05:35 +02:00
Linus Walleij
151a41014b Linux 5.3-rc7
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Merge tag 'v5.3-rc7' into devel

Linux 5.3-rc7
2019-09-05 11:40:54 +02:00
Linus Walleij
f0d1ab0526 gpio: of: Normalize return code variable name
It is confusing to name return variables mixedly "status",
"err" or "ret". I just changed them all to "ret", by personal
preference, to lower cognitive stress.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190716115854.12098-1-linus.walleij@linaro.org
2019-09-04 11:05:27 +02:00
Linus Walleij
d377f56f34 gpio: gpiolib: Normalize return code variable name
It is confusing to name return variables mixedly "status",
"err" or "ret". I just changed them all to "ret", by personal
preference, to lower cognitive stress.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190716091145.8235-1-linus.walleij@linaro.org
2019-09-04 11:04:42 +02:00
Linus Walleij
d2b0919615 gpio: ep93xx: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Cc: H Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Thierry Reding <treding@nvidia.com>
Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190812130000.22252-1-linus.walleij@linaro.org
2019-09-04 10:59:10 +02:00
Linus Walleij
8a6abcd04e gpio: updates for v5.4
- use a helper variable for &pdev->dev in gpio-em
 - tweak the ifdefs in GPIO headers
 - fix function links in HTML docs
 - remove an unneeded error message from ixp4xx
 - use the optional clk_get in gpio-mxc instead of checking the return value
 - a couple improvements in pca953x
 - allow to build gpio-lpc32xx on non-lpc32xx targets
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Merge tag 'gpio-v5.4-updates-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel

gpio: updates for v5.4

- use a helper variable for &pdev->dev in gpio-em
- tweak the ifdefs in GPIO headers
- fix function links in HTML docs
- remove an unneeded error message from ixp4xx
- use the optional clk_get in gpio-mxc instead of checking the return value
- a couple improvements in pca953x
- allow to build gpio-lpc32xx on non-lpc32xx targets
2019-09-03 16:04:19 +02:00
David Jander
438b6c20e6 gpio: pca953x: use pca953x_read_regs instead of regmap_bulk_read
The register number needs to be translated for chips with more than 8
ports. This patch fixes a bug causing all chips with more than 8 GPIO pins
to not work correctly.

Fixes: 0f25fda840a9 ("gpio: pca953x: Zap ad-hoc reg_direction cache")
Cc: Cc: <stable@vger.kernel.org>
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-08-28 12:55:24 +02:00
David Jander
bc624a06f0 gpio: pca953x: correct type of reg_direction
The type of reg_direction needs to match the type of the regmap, which
is u8.

Fixes: 0f25fda840a9 ("gpio: pca953x: Zap ad-hoc reg_direction cache")
Cc: Cc: <stable@vger.kernel.org>
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2019-08-28 12:55:24 +02:00
Linus Walleij
f6a7053ddc gpio: zynq: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190809132649.25176-1-linus.walleij@linaro.org
2019-08-27 13:07:36 +02:00
Linus Walleij
f4e9bcc05f gpio: mt7621: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

This driver requests the IRQ directly in the driver so it
differs a bit from the others.

Cc: Greg Ungerer <gerg@kernel.org>
Cc: Nicholas Mc Guire <hofrat@osadl.org>
Cc: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: René van Dorst <opensource@vdorst.com>
Link: https://lore.kernel.org/r/20190809141116.16403-1-linus.walleij@linaro.org
2019-08-23 12:05:06 +02:00
Christophe JAILLET
b1d64c7139 gpio: ftgpio: Fix an error handling path in 'ftgpio_gpio_probe()'
If 'devm_kcalloc()' fails, we should go through the error handling path,
should some clean-up be needed.

Fixes: 42d9fc7176eb ("gpio: ftgpio: Pass irqchip when adding gpiochip")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/20190822204538.4791-1-christophe.jaillet@wanadoo.fr
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 12:02:34 +02:00
Hongwei Zhang
7db47faae7 gpio: aspeed: Add SGPIO driver
Add SGPIO driver support for Aspeed AST2500 SoC.

Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
Reviewed-by:   Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/1566335128-31498-2-git-send-email-hongweiz@ami.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 11:41:20 +02:00
Stefan Wahren
472a61e777 pinctrl/gpio: Take MUX usage into account
The user space like gpioinfo only see the GPIO usage but not the
MUX usage (e.g. I2C or SPI usage) of a pin. As a user we want
to know which pin is free/safe to use. So take the MUX usage of
strict pinmux controllers into account to get a more realistic
view for ioctl GPIO_GET_LINEINFO_IOCTL.

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Tested-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Link: https://lore.kernel.org/r/20190814110035.13451-1-ramon.fried@linux.intel.com
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 11:09:41 +02:00
Linus Walleij
48057ed184 gpio: Fix irqchip initialization order
The new API for registering a gpio_irq_chip along with a
gpio_chip has a different semantic ordering than the old
API which added the irqchip explicitly after registering
the gpio_chip.

Move the calls to add the gpio_irq_chip *last* in the
function, so that the different hooks setting up OF and
ACPI and machine gpio_chips are called *before* we try
to register the interrupts, preserving the elder semantic
order.

This cropped up in the PL061 driver which used to work
fine with no special ACPI quirks, but started to misbehave
using the new API.

Fixes: e0d897289813 ("gpio: Implement tighter IRQ chip integration")
Cc: Thierry Reding <treding@nvidia.com>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Reported-by: Wei Xu <xuwei5@hisilicon.com>
Tested-by: Wei Xu <xuwei5@hisilicon.com>
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190820080527.11796-1-linus.walleij@linaro.org
2019-08-23 11:00:43 +02:00
Linus Walleij
74639d66e1 gpio: tqmx86: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190809144045.26018-1-linus.walleij@linaro.org
2019-08-23 09:42:22 +02:00
Linus Walleij
e599256ab7 gpio: vf610: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190809141916.20999-1-linus.walleij@linaro.org
2019-08-23 09:41:18 +02:00
Linus Walleij
49751efbf6 gpio: zx: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Jonas Gorski <jogo@openwrt.org>
Cc: Jun Nie <jun.nie@linaro.org>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190809133845.30991-1-linus.walleij@linaro.org
2019-08-23 09:40:44 +02:00
Song Hui
7b732209eb gpio: mpc8xxx: add ls1088a platform special function
ls1028a and ls1088a platform share common special function.
The gpio hardware what they use is the same version.

Signed-off-by: Song Hui <hui.song_1@nxp.com>
Link: https://lore.kernel.org/r/20190808101628.36782-3-hui.song_1@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 09:38:06 +02:00
Marc Zyngier
ac1213b7d7 gpio/ixp4xx: Register the base PA instead of its VA in fwnode
Do not expose the base VA (it appears in debugfs). Instead,
record the PA, which at least can be used to precisely identify
the associated irqchip and domain.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-21 13:33:48 +02:00
Linus Walleij
a7e4214292 gpio: ftgpio: Move hardware initialization
It is probably wise to initialize the hardware before registering
the irq chip.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190819082704.14237-1-linus.walleij@linaro.org
2019-08-20 10:42:07 +02:00
Linus Walleij
eb1e8bd6e3 gpio: Use callback presence to determine need of valid_mask
After we switched the two drivers that have .need_valid_mask
set to use the callback for setting up the .valid_mask,
we can just use the presence of the .init_valid_mask()
callback (or the OF reserved ranges, nota bene) to determine
whether to allocate the mask or not and we can drop the
.need_valid_mask field altogether.

Cc: Benjamin Gaignard <benjamin.gaignard@st.com>
Cc: Amelie Delaunay <amelie.delaunay@st.com>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190819093058.10863-1-linus.walleij@linaro.org
2019-08-20 10:42:07 +02:00
Linus Walleij
c9fc5aff21 gpio: Pass mask and size with the init_valid_mask()
It is more helpful for drivers to have the affected fields
directly available when we use the callback to set up the
valid mask. Change this and switch over the only user
(MSM) to use the passed parameters. If we do this we can
also move the mask out of publicly visible struct fields.

Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190819084904.30027-1-linus.walleij@linaro.or
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-20 10:42:07 +02:00
Uwe Kleine-König
f3260e3ea1 gpio: mockup: don't depend twice on GPIOLIB
config GPIO_MOCKUP is defined in a big if GPIOLIB ... endif block so it
doesn't need to depend explicitly on GPIOLIB.

Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Link: https://lore.kernel.org/r/20190725131002.14597-1-uwe@kleine-koenig.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-20 10:41:59 +02:00
Andreas Kemnade
df451f83e1 gpio: of: fix Freescale SPI CS quirk handling
On the gta04 we see:
spi_gpio: probe of spi_lcd failed with error -2

The quirk introduced in
commit e3023bf80639 ("gpio: of: Handle the Freescale SPI CS")
can also be triggered by a temporary -EPROBE_DEFER and
so "convert" it to a hard -ENOENT.

Disable that conversion by checking for -EPROBE_DEFER.

Fixes: e3023bf80639 ("gpio: of: Handle the Freescale SPI CS")
Suggested-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Link: https://lore.kernel.org/r/20190816165000.32334-1-andreas@kemnade.info
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-17 00:28:50 +02:00
Arnd Bergmann
d64a1fd852 Merge branch 'lpc32xx/multiplatform' into arm/soc
I revisited some older patches here, getting two of the remaining
ARM platforms to build with ARCH_MULTIPLATFORM like most others do.

In case of lpc32xx, I created a new set of patches, which seemed
easier than digging out what I did for an older release many
years ago.

* lpc32xx/multiplatform:
  ARM: lpc32xx: allow multiplatform build
  ARM: lpc32xx: clean up header files
  serial: lpc32xx: allow compile testing
  net: lpc-enet: allow compile testing
  net: lpc-enet: fix printk format strings
  net: lpc-enet: fix badzero.cocci warnings
  net: lpc-enet: move phy setup into platform code
  net: lpc-enet: factor out iram access
  gpio: lpc32xx: allow building on non-lpc32xx targets
  serial: lpc32xx_hs: allow compile-testing
  watchdog: pnx4008_wdt: allow compile-testing
  usb: udc: lpc32xx: allow compile-testing
  usb: ohci-nxp: enable compile-testing

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-08-15 21:35:22 +02:00
Arnd Bergmann
d88ce24a0f gpio: lpc32xx: allow building on non-lpc32xx targets
The driver uses hardwire MMIO addresses instead of the data
that is passed in device tree. Change it over to only
hardcode the register offset values and allow compile-testing.

Link: https://lore.kernel.org/r/20190809144043.476786-6-arnd@arndb.de
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-08-15 21:33:07 +02:00
Linus Walleij
8512ee3192 gpio: aspeed: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Joel Stanley <joel@jms.id.au>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20190809125515.19094-1-linus.walleij@linaro.org
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Tested-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-15 09:59:39 +02:00
Linus Walleij
a2ac3eb365 gpio: hlwd: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20190809140005.11654-1-linus.walleij@linaro.org
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-15 09:57:29 +02:00
Linus Walleij
c7e66e48c0 gpio: xlp: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Jayachandran C <jnair@caviumnetworks.com>
Cc: Kamlakant Patel <kamlakant.patel@broadcom.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190809135119.6946-1-linus.walleij@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-15 09:55:07 +02:00