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8299 Commits

Author SHA1 Message Date
Hawking Zhang
305401e77b drm/amdgpu: force pa_sc_tile_steering_override to 0 for gfx10.3 
pa_sc_tile_steering_override is only programmable for
gfx10.0/10.1/10.2

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Likun Gao
263acd471f drm/amdgpu/gfx10: add gc golden setting for sienna_cichlid 
Add gc golden setting for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
4d72dd12f0 drm/amdgpu: enable JPEG3.0 for Sienna_Cichlid 
By adding JPEG HW block to Sienna_Cichlid

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
b467c4f5b4 drm/amdgpu: enable JPEG3.0 PG and CG for Sienna_Cichlid 
By setting up the flags to the ASIC

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
b52e271e15 drm/amdgpu: add Sienna_Cichlid JPEG PG and CG support 
This is for static powergating and clockgating

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
dfd57dbf44 drm/amdgpu: add JPEG3.0 support for Sienna_Cichlid 
With basic IP block functions and ring functions

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
b8f10585cb drm/amdgpu: enable VCN3.0 for Sienna_Cichlid 
By adding VCN HW block to Sienna_Cichlid

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
265120abc0 drm/amdgpu: add Sienna_Cichlid VCN to the VCN family 
By adding Sienna_Cichlid VCN firmware

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
e823be13db drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid 
By setting up the flags to the ASIC

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
fedac0155a drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2) 
This is for static powergating and clockgating

v2: fix registers (Alex)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Leo Liu
cf14826cdf drm/amdgpu: add VCN3.0 support for Sienna_Cichlid 
With basic IP block functions and ring functions

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Likun Gao
25fc05648f drm/amdgpu/mes: correct register offset for sienna_cichlid 
Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Likun Gao
83a0c342e0 drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid 
The number of queue per pipe for mec on sienna_cichlid should be 4.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Jack Xiao
a346ef86a9 drm/amdgpu: add mes block to sienna_cichlid 
Add mes block support to sienna_cichlid.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:09 -04:00
Jack Xiao
9ed60748fb drm/amdgpu/mes10.1: update mes initialization 
Update mes initialization sequence.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
03195e8063 drm/amdgpu: no need to set up GPU scheduler for mes ring 
As mes ring directly submits to hardwared,
it's no need to set up GPU scheduler for mes ring.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
93fd978b2b drm/amdgpu/psp: convert amdgpu mes ucode type 
Convert to psp defined ucode item, so that psp can recognize them.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
aa1faaa1fc drm/amdgpu: upload mes firmware to gpu buffer 
Copy mes firmware to gpu buffer.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
6b8199fc1a drm/amdgpu/mes10.1: copy mes fw info into global fw array 
Copy mes firmware info into into global fw array, preparing
for fw front door loading.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
f85f1864b8 drm/amdgpu/mes10.1: add sienna_cichlid mes firmware support 
Add sienna_cichlid mes firmware support.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
7a9b4fd416 drm/amdgpu/mes10.1: implement setting hardware resources 
The routine is implemented to generate mes command to
assign the hardware resources which can be scheduled
to mes.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
3e62add5ec drm/amdgpu/mes10.1: implement querying the scheduler status 
The routine is implemented to generate mes command
to query the status of hardware scheduler.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
bc2a28120d drm/amdgpu/mes10.1: implement removing hardware queue 
The routine is implemented to generate mes command to remove
a specified hardware queue.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
e8bb73e0e4 drm/amdgpu/mes10.1: implement adding hardware queue 
The routine is implemented to generate mes command
to install a hardware queue.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
29ce0f6f3c drm/amdgpu/mes10.1: add the helper function for mes command submission 
The helper function is used to submit mes command and poll waiting
for the command completion.

v2: replaced with amdgpu_fence_wait_polling to wait.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
3f63345d38 drm/amdgpu/mes10.1: add the mes fw api 
Add the definitions of mes commands.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
e25c0dcd0d drm/amdgpu/mes10.1: enable the mes ring during initialization 
Enable the mes ring during mes block initialization.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
1c0d96b0d7 drm/amdgpu/mes10.1: install mes queue via kiq 
Install mes queue via kiq. Disable it temporarily
until it's workable.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
debce56dde drm/amdgpu/mes10.1: install mes queue by register programming 
Directly writing mes queue registers to set up it.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
74d250fb11 drm/amdgpu/mes10.1: initialize the mqd 
Initialize the mqd according to mes ring setup.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
52d6bb128e drm/amdgpu/mes10.1: allocate mqd buffer 
Allocate mqd buffer preparing for mes queue setup.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
1513e24aa4 drm/amdgpu/mes10.1: implement the ring functions of mes specific 
Implement mes ring functions and set up them.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:08 -04:00
Jack Xiao
7b2513a16c drm/amdgpu/mes10.1: initialize the software part of mes ring 
Do the software initialization on the mes ring.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Jack Xiao
11f6f11da0 drm/amdgpu/mes10.1: allocate the eop buffer 
eop buffer will be used for mes queue setup.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Jack Xiao
3bbd31e0f4 drm/amdgpu/mes: update some mes definitions 
Update some mes definitions.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Jack Xiao
55611b507f drm/amdgpu: avoid dereferencing a NULL pointer 
Check if irq_src is NULL to avoid dereferencing a NULL pointer,
for MES ring is uneccessary to recieve an interrupt notification.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Jack Xiao
cdca797945 drm/amdgpu: add the ring type definition of MES 
Add a new ring type definition.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Jack Xiao
2051923272 drm/amdgpu: assign the doorbell index to mes ring 
MES ring will use the assigned doorbell index for
command submission.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Leo Liu
71ac5c1fac drm/amdgpu: add 2rd VCN instance doorbell support 
Sienna_Cichlid have 2 VCN instances, using different register for range

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Likun Gao
56304e72af drm/amdgpu: add psp block load condition for sienna_cichlid 
Enable PSP block for firmware loading and other security
setup only when amdgpu use PSP load type to load ucode.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Likun Gao
920a4cd3f3 drm/amdgpu: add gmc cg support for sienna_cichlid 
Add gmc clockgating support for sienna_cichlid.
The athub version used for sienna_cichlid is v2.1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Likun Gao
45d76eebd8 drm/amdgpu: add support for athub v2.1 
Add athub v2.1 function and support to compile it.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Yong Zhao
9822ac8f85 drm/amdgpu: Use variable instead of constant for sdma doorbell range 
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Likun Gao
c399dfcb0e drm/amdgpu: update SDMA 5.2 microcode init 
Removed loading duplicate instances of SDMA FW for Sienna_Cichlid,
As sienna_cichlid only use a single image for all instances.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Likun Gao
5aa023506a drm/amdgpu: enable psp ip block for sienna_cichlid 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Likun Gao
64f2d805a1 drm/amdgpu: skip for reroute ih for sienna_cichlid psp ring init currently 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Likun Gao
344fed0b27 drm/amdgpu/psp: add psp support for sienna_cichlid 
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Likun Gao
bfdb68eca2 drm/amdgpu: skip ASD fw load for sienna_cichlid 
Skip ASD FW load for sienna_cichlid currently.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:59:07 -04:00
Likun Gao
b07e5c60e4 drm/amdgpu/powerplay: add smu block for sienna_cichlid 
Add SMU block for sienna_cichlid with psp load type.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2020-07-01 01:58:55 -04:00
Dave Airlie
f75020fcb9 Merge tag 'drm-misc-next-2020-06-26' of git://anongit.freedesktop.org/drm/drm-misc into drm-next 
drm-misc-next for v5.9:

Cross-subsystem Changes:
- Improve dma-buf docs.

Core Changes:
- Add NV15, Q410, Q401 yuv formats.
- Add uncompressed AFBC modifier.
- Add DP helepr for reading Ignore MSA from DPCD.
- Add missing panel type for some panels
- Optimize drm/mm hole handling.
- Constify connector to infoframe functions.
- Add debugfs for VRR monitor range.

Driver Changes:
- Assorted small bugfixes in panfrost, malidp, panel/otm8009a.
- Convert tfp410 dt bindings to yaml, and rework time calculations.
- Add support for a few more simple panels.
- Cleanups and optimizations for ast.
- Allow adv7511 and simple-bridge to be used without connector creation.
- Cleanups to dw-hdmi function prototypes.
- Remove enabled bool from tiny/repaper and mipi-dbi, atomic handles it.
- Remove unused header file from dw-mipi-dsi
- Begin removing ttm_bo->offset.

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/b1e53620-7937-895c-bfcf-ed208be59c7c@linux.intel.com
 2020-06-30 14:04:00 +10:00