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[Why]
During SetPathMode and UpdatePlanes, the plane state can be null. We default
to linear swizzle mode when plane state is null. This resulted in bandwidth
validation failing when trying to set 8K60 mode (which previously passed validation
during rebuild timing list).
[How]
Change the default swizzle mode from linear to 4kb_s and update pitch accordingly.
Signed-off-by: George Shen <george.shen@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[How]
Use dc_is_hdmi_signal to determine signal type.
Signed-off-by: JinZe.Xu <JinZe.Xu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Sink OUI supported cap is not set so driver skips programming it.
[How]
Revert the change the skips OUI programming if the cap is not set
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
use correct logger context
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Test expects that we also read HPD_IRQ_VECTOR when checking for
symbol loss as well lane status.
[How]
Read bytes 0x200-0x205 instead of just 0x202-0x205
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Feature requires synchronization of dig, pipe, and cursor locking
between driver and fw.
[How]
Set flag to force psr to use hw lock mgr.
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
ramp_up_dispclk_with_dpp is to change dispclk, dppclk and dprefclk
according to bandwidth requirement. call stack: rv1_update_clocks -->
update_clocks --> dcn10_prepare_bandwidth / dcn10_optimize_bandwidth
--> prepare_bandwidth / optimize_bandwidth. before change dcn hw,
prepare_bandwidth will be called first to allow enough clock,
watermark for change, after end of dcn hw change, optimize_bandwidth
is executed to lower clock to save power for new dcn hw settings.
below is sequence of commit_planes_for_stream:
step 1: prepare_bandwidth - raise clock to have enough bandwidth
step 2: lock_doublebuffer_enable
step 3: pipe_control_lock(true) - make dchubp register change will
not take effect right way
step 4: apply_ctx_for_surface - program dchubp
step 5: pipe_control_lock(false) - dchubp register change take effect
step 6: optimize_bandwidth --> dc_post_update_surfaces_to_stream
for full_date, optimize clock to save power
at end of step 1, dcn clocks (dprefclk, dispclk, dppclk) may be
changed for new dchubp configuration. but real dcn hub dchubps are
still running with old configuration until end of step 5. this need
clocks settings at step 1 should not less than that before step 1.
this is checked by two conditions: 1. if (should_set_clock(safe_to_lower
, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) ||
new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz)
2. request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz
the second condition is based on new dchubp configuration. dppclk
for new dchubp may be different from dppclk before step 1.
for example, before step 1, dchubps are as below:
pipe 0: recout=(0,40,1920,980) viewport=(0,0,1920,979)
pipe 1: recout=(0,0,1920,1080) viewport=(0,0,1920,1080)
for dppclk for pipe0 need dppclk = dispclk
new dchubp pipe split configuration:
pipe 0: recout=(0,0,960,1080) viewport=(0,0,960,1080)
pipe 1: recout=(960,0,960,1080) viewport=(960,0,960,1080)
dppclk only needs dppclk = dispclk /2.
dispclk, dppclk are not lock by otg master lock. they take effect
after step 1. during this transition, dispclk are the same, but
dppclk is changed to half of previous clock for old dchubp
configuration between step 1 and step 6. This may cause p-state
warning intermittently.
[How]
for new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz, we
need make sure dppclk are not changed to less between step 1 and 6.
for new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz,
new display clock is raised, but we do not know ratio of
new_clocks->dispclk_khz and clk_mgr_base->clks.dispclk_khz,
new_clocks->dispclk_khz /2 does not guarantee equal or higher than
old dppclk. we could ignore power saving different between
dppclk = displck and dppclk = dispclk / 2 between step 1 and step 6.
as long as safe_to_lower = false, set dpclk = dispclk to simplify
condition check.
CC: Stable <stable@vger.kernel.org>
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Each asic can optimize best based on its capabilities
[How]
Optimizing timing for a new pixel clock
Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Programming DCN is explicitly forbidden during idle optimzations allowed
state. Existing implemenation relies on OS/DM, which is not robust. Instead
DC should sequence this.
Note that DC will not re-enter idle optimized state on its own, it is only
responsible for catching out of sequence calls. It is still DM
responsibility to sequence appropriate for optimized power, but this change
removes the requirement for DM to cover the .1% case.
[How]
- elevate updates during idle optimized state to full updates
- disable idle power optimizations prior to programming
Signed-off-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
With all DCE6 specific macros, register, masks in place
dce60_resource.c may use them and become independent from DCE8 headers
[How]
(v1) Changelog:
- use DCE6 headers for registers and masks, remove the DC8 headers
- remove 7th Display Controller/Encoder register instances (DCE6 has only 6)
- use DCE6 specific watermark programming registers (DPG_PIPE_ARBITRATION_CONTROL3)
- use DCE6 specific input pixel processing registers shift/mask
- use DCE6 specific transform registers shift/mask
- use DCE6 specific link encoder registers shift/mask
- use DCE6 specific output pixel processing registers shift/mask
- use DCE6 specific audio registers shift/mask
- use DCE6 specific dmcu registers shift/mask
- use DCE6 specific hwseq registers shift/mask
- use DCE6 specific mem input registers shift/mask
(v2) Changelog:
- use DCE6 ad hoc dce60_mem_input_construct() function
- use DCE6 ad hoc dce60_transform_construct() function
(v3) Changelog:
- use DCE6 ad hoc dce60_ipp_construct() function
(v4) Changelog:
- use DCE6 ad hoc dce60_link_encoder_construct() function
(v5) Changelog:
- use DCE6 ad hoc dce60_opp_construct() function
(v6) Changelog:
- use DCE6 ad hoc dce60_audio_create() function
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DCE6 has CRTC_PREFETCH_EN bit in CRTC_CONTROL register
DCE6 has no CRTC_LEGACY_REQUESTOR_EN bit in CRTC_START_LINE_CONTROL register
DCE6 has no CRTC_CRC_CNTL register
[How]
Modify dce60_timing_generator_enable_advanced_request() function
Add dce60_configure_crc() function and dce60_is_tg_enabled() kept as static
Use dce60_configure_crc() function in dce60_tg_funcs
v2: remove unused variable (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
kernel WARNING due to use of .cursor_lock = dce_pipe_control_lock inherited by dce110
[How]
DCE6 set .cursor_lock = dce60_pipe_control_lock
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DCE6 has no bottom_pipe and no Blender HW
DCE6 needs 'blank_target' set to false in order to turn on the display
DCE6 has a specific dce60_pipe_control_lock() fuction that is a no op
[How]
Add DCE6 specific functions with needed private dce60_* dependent fuctions
Comment DCE6 specific CTRC program visibility implementation
Fix a typo in the initial header includes comment 's/DCE8/DCE6/g'
Use dce60_apply_ctx_for_surface() in dce60_hw_sequencer_construct
Use dce60_pipe_control_lock() in dce60_hw_sequencer_construct
v2: add missing return type (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DCE6 has specific SCL_HORZ_FILTER_INIT_{LUMA_RGB,CHROMA} registers
In DCE6 h_init_luma and h_init_chroma initialization is required
Some DCE6 specific SCL_{HORZ,VERT}_FILTER_CONTROL masks were not listed
[How]
Add the registers and masks in dce_transform.h
Add DCE6 specific struct sclh_ratios_inits in dce_transform.h
Add dce60_calculate_inits() function
Add dce60_program_scl_ratios_inits() function
Fix dce60_transform_set_scaler() function
v2: remove unused variable (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DCE6 has no SCL_MODE and no SCL_{HORZ,VERT}_FILTER_INIT registers
DCE6 has no SCL_BOUNDARY_MODE bit in SCL_CONTROL register
DCE6 has Line Buffer programming registers (DC_LB_MEMORY_SPLIT,DC_LB_MEM_SIZE)
DCE6 DATA_FORMAT register has only INTERLEAVE_EN bit
DCE6 has no Out Clamp Control programming registers (OUT_CLAMP_CONTROL_*)
[How]
Add DCE6 specific macros definitions for XFM registers and masks
Add DCE6 specific registers to dce_transform_registers struct
Add DCE6 specific masks to dce_transform_mask struct
DCE6 XFM macros/structs changes will avoid buiding errors when using DCE6 headers
Add dce60_setup_scaling_configuration() w/o missing Scaling registers/bit programming
Add dce60_transform_set_scaler() using DCE6 Line Buffer programming registers
Add dce60_program_bit_depth_reduction() w/o Out Clamp Control programming
Add dce60_transform_set_pixel_storage_depth() use dce60_program_bit_depth_reduction()
Use dce60_transform_set_scaler() in dce60_transform_funcs
Use dce60_transform_set_pixel_storage_depth() in dce60_transform_funcs
Add DCE6 specific dce60_transform_construct
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DCE6 has no FMT_TRUNCATE_MODE bit in FMT_BIT_DEPTH_CONTROL register
DCE6 has no FMT_CLAMP_COMPONENT_{R,G,B} registers
DCE6 has no FMT_SUBSAMPLING_{MODE,ORDER} bits in FMT_CONTROL register
[How]
Add DCE6 specific macros definitions for OPP registers and masks
DCE6 OPP macros will avoid buiding errors when using DCE6 headers
Add dce60_set_truncation() w/o FMT_TRUNCATE_MODE bit programming
Add dce60_opp_set_clamping() w/o Format Clamp Component programming
Add dce60_opp_program_fmt() w/o Format Subsampling bits programming
Add dce60_opp_program_bit_depth_reduction() with dce60_set_truncation
Use dce60_opp_program_fmt() in dce60_opp_funcs
Use dce60_opp_program_bit_depth_reduction() in dce60_opp_funcs
Add DCE6 specific dce60_opp_construct
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DCE6 has DPG_PIPE_ARBITRATION_CONTROL3 register for Line Buffer watermark selection
DCE6 has STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK mask for Stutter watermark selection
DCE6 has NB_PSTATE_CHANGE_WATERMARK_MASK mask for North Bridge watermark selection
DCE6 has no GRPH_MICRO_TILE_MODE mask
DCE6 has no HW_ROTATION register
[How]
Add DCE6 specific macros definitions for MI registers and masks
Add DCE6 specific registers to dce_mem_input_registers struct
Add DCE6 specific masks to dce_mem_input_masks struct
DCE6 MI macros/structs changes will avoid buiding errors when using DCE6 headers
Add dce60_program_urgency_watermark() function
Add dce60_program_nbp_watermark() function
Add dce60_program_stutter_watermark() function
Add dce60_mi_program_display_marks() function w/ new DCE6 watermark programming
Add DCE6 specific tiling programming and modify DCE8 case
Add dce60_program_size() fuction w/o Rotation processing
Add dce60_mi_program_surface_config() fuction
Use dce60_mi_program_display_marks() in dce60_mi_funcs
Use dce60_mi_program_surface_config() in dce60_mi_funcs
Add DCE6 specific dce60_mem_input_construct
v2: remove unused variable (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DCE6 has no DP_DPHY_SCRAM_CNTL register
[How]
Add DCE6 specific macros definitions for LE registers
DCE6 LE macros will avoid buiding errors when using DCE6 headers
Add dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2() w/o Scramble Control programming
Add dce60_set_dp_phy_pattern_passthrough_mode() w/o Scramble Control programming
Add dce60_configure_encoder() w/o Scramble Control programming
Add dce60_link_encoder_enable_dp_output() w/ dce60_configure_encoder
Add dce60_link_encoder_enable_dp_mst_output() w/ dce60_configure_encoder
Add dce60_link_encoder_dp_set_phy_pattern() w/ dce60_set_dp_phy_pattern_passthrough_mode
Use dce60_link_encoder_enable_dp_output() in dce60_lnk_enc_funcs
Use dce60_link_encoder_enable_dp_mst_output() in dce60_lnk_enc_funcs
Use dce60_link_encoder_dp_set_phy_pattern() in dce60_lnk_enc_funcs
Add DCE6 specific dce60_link_encoder_construct
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DCE6 does not have CURSOR2_DEGAMMA_MODE bit in DEGAMMA_CONTROL register
[How]
Add DCE6 specific macros definitions for IPP masks
DCE6 IPP macros will avoid buiding errors when using DCE6 headers
Add dce60_ipp_set_degamma() function w/o Cursor2 Degamma programming
Use dce60_ipp_set_degamma() in ipp_funcs dce60_ipp_funcs
Add DCE6 specific dce60_ipp_construct
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DCE6 has no BLND_CONTROL register for Blender HW programming
DCE6 has no BLND_V_UPDATE_LOCK register for Pipe Locking
[How]
Add DCE6 specific macros definitions for HWSEQ registers and masks
DCE6 HWSEQ macros will avoid buiding errors when using DCE6 headers
Add dce60_pipe_control_lock() stub with no op
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DCE6 has no SMU_INTERRUPT_CONTROL register, but it's used for DCN10 and later
[How]
Add DCE6 specific macros definitions for DMCU registers and masks
DCE6 DMCU macros will avoid buiding errors when using DCE6 headers
There is no other change needed in dce_dcmu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE register
[How]
Add DCE6 specific macros definitions for AUD masks
DCE6 AUD macros will avoid buiding errors when using DCE6 headers
Add dce60_aud_wall_dto_setup() w/o 512*Fs programming
Use dce60_aud_wall_dto_setup() in dce60_funcs
Add DCE specific dce60_audio_create
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Issue in the Mouse cursor size in Linux Desktop Environments
[How]
In DCE6 dc->caps.max_cursor_size need to be set as 64 instead of 128
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(v1) Changelog
[Why]
After commit c69dd2d "drm/amd/display: Refactor clk_mgr functions"
dc/clk_mgr requires these changes to add SI parts support
Necessary to avoid hitting default: ASSERT(0); /* Unknown Asic */
that would cause kernel freeze
[How]
Add case statement for FAMILY_SI chipsets
(v2) Changelog
[Why]
DCE6 has no DPREFCLK_CNTL register
[How]
Add DCE6 specific macros definitions for CLK registers and masks
Add DCE6 specific dce60/dce60_clk_mgr.c for DCE6 customization
Code style: reuse all the public functions in dce100/dce_clk_mgr.h header
Code style: use dce60_* static functions as per other DCE implementations
Add dce60_get_dp_ref_freq_khz() w/o using DPREFCLK_CNTL register
Use dce60_get_dp_ref_freq_khz() function in dce60_funcs
Add DCE6 specific dce60_clk_mgr_construct
dc/clk_mgr/dce_clk_mgr.c: use dce60_clk_mgr_construct for FAMILY_SI chipsets
Add Makefile rules for dce60_clk_mgr.o target conditional to CONFIG_DRM_AMD_DC_SI
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
irq service requires changes for DCE6 support
[How]
(v1) DCE6 targets are added replicating existing DCE8 implementation.
due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
dce/dce_8_0_{d,sh_mask}.h used instead of dce/dce_6_0_{d,sh_mask}.h
(v2) DCE6 headers used adding the necessary vblank irq registers
(INT_MASK and VBLANK_STATUS) and vblank irq masks as implemented
in amdgpu driver.
Add vblank_irq_info_funcs_dce60 with .set and .ack as per commit
b10d51f ("drm/amd/display: Add interrupt entries for VBLANK isr.")
and use it in vblank_int_entry(reg_num) macro definition
(v3) updated due to following kernel 5.3 commit:
4fc4dca ("drm/amd: drop use of drmp.h in os_types.h")
(v4) updated due to following kernel 5.6 commit:
d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
hw_factory.c requires changes for DCE6 support
[How]
DCE6 targets added replicating and adapting existing DCE8 implementation.
(v2) changes due to following commit:
91db931 ("drm/amd/display: refactor gpio to allocate hw_container in constructor")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
command_table_helper.c requires changes for DCE6 support
[How]
DCE6 targets added replicating and adapting the existing DCE8 implementation.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
resource_parse_asic_id() and dc_create_resource_pool() are missing SI/DCE6 cases
[How]
SI/DCE6 cases support added using existing DCE8 implementation as a reference
(v2) updated due to following kernel 5.2 commit:
d9673c9 ("drm/amd/display: Pass init_data into DCN resource creation")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DCE6 chipsets have a lot in common with DCE8, let's start from this
[How]
DCE6 targets are added replicating existing DCE8 implementation.
NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
initial build prototype due to missing DCE6 macros/registers/masks
DCE6 specific macros/registers/masks will be added with later commits
(v2b) removed dce_version cases in dc/dce/dce_clock_source.c and
updated dce60 due to following kernel 5.0 commits:
24f7dd7 ("drm/amd/display: move pplib/smu notification to dccg block")
9566b67 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead")
4244381 ("drm/amd/display: clean up base dccg struct")
4c5e8b5 ("drm/amd/display: split dccg clock manager into asic folders")
84e7fc0 ("drm/amd/display: rename dccg to clk_mgr")
77f6916 ("drm/amd/display: Remove duplicate header")
9f7ddbe ("drm/amd/display: fix optimize_bandwidth func pointer for dce80")
4ece61a ("drm/amd/display: set clocks to 0 on suspend on dce80")
(v3b) updated dce60 due to following kernel 5.1 commits:
380604e ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks")
32e6136 ("drm/amd/display: Fix 64-bit division for 32-bit builds")
1877ccf ("drm/amd/display: Change from aux_engine to dce_aux")
c69dffa ("drm/amd/display: fix eDP fast bootup for pre-raven asic")
(v4b) updated dce60 due to following kernel 5.2 commits:
e5c4197 ("drm/amd/display: Add plane capabilities to dc_caps")
813d20d ("drm/amd/display: Fix multi-thread writing to 1 state")
ea36ad3 ("drm/amd/display: expand plane caps to include fp16 and scaling capability")
afcd526 ("drm/amd/display: Add fast_validate parameter")
(v5b) updated dce60 due to following kernel 5.3 commits:
e7e10c4 ("drm/amd/display: stop external access to internal optc sync params")
78cc70b ("drm/amd/display: Engine-specific encoder allocation")
dc88b4a ("drm/amd/display: make clk mgr soc specific")
4fc4dca ("drm/amd: drop use of drmp.h in os_types.h")
(v6b) updated dce60 due to following kernel 5.4 commits:
54a9bcb ("drm/amd/display: Fix a typo - dce_aduio_mask --> dce_audio_mask")
9adc805 ("drm/amd/display: make firmware info only load once during dc_bios create")
(v7b) updated dce60 due to following kernel 5.5 commits:
cabe144 ("drm/amd/display: memory leak")
8276dd8 ("drm/amd/display: update register field access mechanism")
f6040a4 ("drm/amd/display: configurable aux timeout support")
bf7f5ac ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x")
(v8b) updated dce60 due to following kernel 5.6 commits:
d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs")
f42ea55 ("drm/amd/display: add separate of private hwss functions")
(v9b) updated dce60 due to following kernel 5.8 commits:
bba8289 ("drm/amd/display: code clean up in dce80_hw_sequencer.c")
904fb6e ("drm/amd/display: move panel power seq to new panel struct")
d4caa72 ("drm/amd/display: change from panel to panel cntl")
(v10) Fix up PLL handling for DCE6:
DCE6.0 supports 2 PLLs. DCE6.1 supports 3 PLLs. (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use DCN21 functions instead of DCE110
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Some monitors could suffer symbol unlock but cannot send HPD IRQ to
notic source device to handle link loss. This makes monitor stuck in
abnormal status and causes black screen.
[How]
According to the suggestion from scalar vendor, to check lane status
again after link training done. That can improve the comaptibility
from current production monitors.
Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
In dcn3_update_clocks there are situations where dppclk is not
lowered (i.e. stays the same), but DTO still needs to be increased
before we program pipe frontend (i.e. in prepare_bandwidth). If we
don't program the new DTO value before we program the pipe,
we will underflow as soon as the pipe lock is released until the
next call to dcn3_update_clocks where the DTO is updated.
[How]
Remove dppclk check before programming new DTO value.
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Struct dcn_dsc_state is used for reading current state
and parameters of DSC on a pipe, the target rate parameter
uses bytes per pixel even though its reading BITS_PER_PIXEL
register.
[How]
Changing it to Bits Per Pixel for consistency.
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
This change replaces older looping code in favor of these functions.
[How]
There are built in functions for extracting global sync params
during mode validation now.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The variable result is being initialized with a value that is never read
and it is being updated later with a new value. The initialization is
redundant and can be removed.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fix below warnings reported by coccicheck:
./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:557:2-7: WARNING: NULL check before some freeing functions is not needed.
Fixes: 4d55b0dd1cdd ("drm/amd/display: Add DCN3 CLK_MGR")
Signed-off-by: Li Heng <liheng40@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Implement an interface to obtain plane size caps
[How]
Add min_width, min_height fields to dc_plane_cap structure.
Set values to 16x16 for discrete ASICs, and 64x64 for others.
Signed-off-by: Igor Kravchenko <Igor.Kravchenko@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
On DCN20, Some features would not be activated when ALLM was turned on.
TV seemed to activate only the latest info packet sent, and the ALLM
info packet was sent after the VSIF info packet.
The packet indices was also inconsistent between DCN10 and DCN20.
[how]
Change the packet indices of DCN20 to match those of DCN10.
This makes them consistent and also makes the vendor info packet
be sent after the hfvsif info packet.
Signed-off-by: Naveed Ashfaq <Naveed.Ashfaq@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
dcn20_add_dsc_to_stream_resource is accessed in amdgpu_dm directly.
This creates build error for configuration with DCN disabled.
[How]
Make the function available through a resource pool function so
that dcn20 function need not be called directly.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
The capability fields are reserved for DSC branch
only to report the capability related to the
branch's DSC decoder.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
To support V3
[How]
Generate new VSIF for V3
Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
Need to add new parameters to debugfs logging so
we will know what parameters DSC is using for
debug purposes. So we are adding a read function
in debugfs to read DSC status registers
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Scaler vendor confirmed the 5ms was not helpful so no point in keeping
it.
[How]
Revert 5ms delay after setting training pattern.
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The "stream" pointer can't be NULL and it's dereferenced on the line
before so the check doesn't make sense.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
