aeaa0bfe89
PCI: dwc: Move N_FTS setup to common setup
...
The Designware controller has common registers to set number of fast
training sequence ordered sets. The Artpec6, Intel, and Tegra driver
initialize these register fields. Let's move the initialization to the
common setup code and drivers just have to provide the value.
There's a slight change in that the common clock mode N_FTS field is
now initialized. Previously only the Intel driver set this. It's not
clear from the code if common clock mode is used in the Artpec6 or Tegra
driver. It depends on the DWC configuration. Given the field is not
initialized while the others are, it seems unlikely common clock mode
is used.
Link: https://lore.kernel.org/r/20200821035420.380495-40-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org >
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Cc: Jesper Nilsson <jesper.nilsson@axis.com >
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Cc: Bjorn Helgaas <bhelgaas@google.com >
Cc: Jingoo Han <jingoohan1@gmail.com >
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com >
Cc: Thierry Reding <thierry.reding@gmail.com >
Cc: Jonathan Hunter <jonathanh@nvidia.com >
Cc: linux-tegra@vger.kernel.org
2020-09-10 16:50:53 +01:00
d439e7edd1
PCI: dwc/intel-gw: Drop unused max_width
...
'max_width' is read, but never used, so let's remove it.
Link: https://lore.kernel.org/r/20200821035420.380495-39-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org >
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Cc: Dilip Kota <eswara.kota@linux.intel.com >
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Cc: Bjorn Helgaas <bhelgaas@google.com >
2020-09-10 16:50:53 +01:00
cf854be2d9
PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup()
...
The PCI_CAP_ID_EXP offset is only needed by intel_pcie_link_setup(), so
let's retrieve it there and avoid storing the offset.
Link: https://lore.kernel.org/r/20200821035420.380495-38-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org >
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Cc: Dilip Kota <eswara.kota@linux.intel.com >
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Cc: Bjorn Helgaas <bhelgaas@google.com >
2020-09-10 16:50:53 +01:00
b02b06a74b
PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' property
...
A driver doesn't need to check for DT 'device_type' property, so let's
remove the check.
Link: https://lore.kernel.org/r/20200821035420.380495-37-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org >
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Cc: Dilip Kota <eswara.kota@linux.intel.com >
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Cc: Bjorn Helgaas <bhelgaas@google.com >
2020-09-10 16:50:53 +01:00
441e48fdf0
PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code
...
The Intel driver is the only one to set PORT_LINK_DLL_LINK_EN. The
default value is set and it seems pretty certain that enabling link
initialization is always required. Maybe it could just be dropped from
the Intel driver, but lets move setting it into the common code to be
sure.
Link: https://lore.kernel.org/r/20200821035420.380495-36-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org >
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Cc: Dilip Kota <eswara.kota@linux.intel.com >
Cc: Jingoo Han <jingoohan1@gmail.com >
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com >
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Cc: Bjorn Helgaas <bhelgaas@google.com >
2020-09-10 16:50:53 +01:00
39bc500650
PCI: dwc: Centralize link gen setting
...
keystone would force gen2 if no DT property. Now it relies on the
PCI_EXP_LNKCAP value.
Link: https://lore.kernel.org/r/20200821035420.380495-35-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org >
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Cc: Kishon Vijay Abraham I <kishon@ti.com >
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Cc: Bjorn Helgaas <bhelgaas@google.com >
Cc: Richard Zhu <hongxing.zhu@nxp.com >
Cc: Lucas Stach <l.stach@pengutronix.de >
Cc: Shawn Guo <shawnguo@kernel.org >
Cc: Sascha Hauer <s.hauer@pengutronix.de >
Cc: Pengutronix Kernel Team <kernel@pengutronix.de >
Cc: Fabio Estevam <festevam@gmail.com >
Cc: NXP Linux Team <linux-imx@nxp.com >
Cc: Murali Karicheri <m-karicheri2@ti.com >
Cc: Jingoo Han <jingoohan1@gmail.com >
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com >
Cc: Stanimir Varbanov <svarbanov@mm-sol.com >
Cc: Andy Gross <agross@kernel.org >
Cc: Bjorn Andersson <bjorn.andersson@linaro.org >
Cc: Pratyush Anand <pratyush.anand@gmail.com >
Cc: Thierry Reding <thierry.reding@gmail.com >
Cc: Jonathan Hunter <jonathanh@nvidia.com >
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
2020-09-10 16:50:54 +01:00
936fa5cd7b
PCI: dwc: Convert to devm_platform_ioremap_resource_byname()
...
Use devm_platform_ioremap_resource_byname() to simplify the code
since it contains platform_get_resource_byname() and
devm_ioremap_resource() respectively.
Link: https://lore.kernel.org/r/20200708164013.5076-1-zhengdejin5@gmail.com
Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com >
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com >
Reviewed-by: Rob Herring <robh@kernel.org >
2020-07-17 17:15:08 +01:00
558c1225a2
PCI: dwc: intel: Make intel_pcie_cpu_addr() static
...
Fix the following sparse warning:
drivers/pci/controller/dwc/pcie-intel-gw.c:456:5: warning: symbol
'intel_pcie_cpu_addr' was not declared. Should it be static?
Link: https://lore.kernel.org/r/20200415084953.6533-1-yanaijie@huawei.com
Reported-by: Hulk Robot <hulkci@huawei.com >
Signed-off-by: Jason Yan <yanaijie@huawei.com >
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
2020-05-22 15:05:23 +01:00
ed22aaaede
PCI: dwc: intel: PCIe RC controller driver
...
Add support to PCIe RC controller on Intel Gateway SoCs.
PCIe controller is based of Synopsys DesignWare PCIe core.
Intel PCIe driver requires Upconfigure support, Fast Training
Sequence and link speed configurations. So adding the respective
helper functions in the PCIe DesignWare framework.
It also programs hardware autonomous speed during speed
configuration so defining it in pci_regs.h.
Also, mark Intel PCIe driver depends on MSI IRQ Domain
as Synopsys DesignWare framework depends on the
PCI_MSI_IRQ_DOMAIN.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com >
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com >
Reviewed-by: Andrew Murray <andrew.murray@arm.com >
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com >
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com >
2020-01-09 11:57:18 +00:00
