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Currently, overo-related include files are organized as follow:
omap3-overo.dtsi
|
|
omap34xx.dtsi omap3-overo-tobi-common.dtsi omap36xx.dtsi
| | | |
--------------- ---------------
| |
omap3-overo-tobi.dts omap3-overo-storm-tobi.dts
This is unpractical when one has to deal with SoC-specific pinmux
belonging to the omap3_pmx_core2 (defined in omap34xx/omap36xx),
for pins related to the processor board. With the current
hierarchy, such pinmux has to be defined in the expansion board's
.dts, which is not logical.
This patches reorganizes the files to add (yet another) abstraction
layer between the processor and the expansion boards.
omap34xx.dtsi omap3-overo-base.dtsi omap36xx.dtsi
| | | |
--------------- ---------------
| |
omap3-overo.dtsi omap3-overo-storm.dtsi
| |
-------- ------
| omap3-overo-tobi-common.dtsi |
| | | |
--------------- ---------------
| |
omap3-overo-tobi.dts omap3-overo-storm-tobi.dts
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The IOMMU DT nodes have been added for the DSP and IPU
subsystems. The MMUs in OMAP5 are identical to those in
OMAP4, including the bus error back capability on IPU.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the IOMMU nodes for the DSP and IPU subsystems. The MMU
within the IPU sub-system also supports a bus error back
capability, not available on the DSP MMU.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
[s-anna@ti.com: IPU bus error back addition]
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the DT node for the IOMMU within the DSP subsystem. The entry
is disabled to keep in line with the hwmod usage as intended by
the deprecated CONFIG_OMAP_IOMMU_IVA2 flag.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
[s-anna@ti.com: split the entry and disable the node]
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Update the IOMMU node for the camera subsystem as per the
OMAP IOMMU bindings.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
[s-anna@ti.com: corrected interrupt number]
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OMAP5 has the same iommus as OMAP4, so extend the OMAP4
iommu pdata quirks for OMAP5 as well.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
A new MMU hwmod class and data structures are created
to represent the MMUs within the IPU and DSP processor
subsystems in OMAP5. The MMUs in OMAP5 are identical to
those in OMAP4.
Cc: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The OMAP iommu driver performs the reset management for the
iommu instances in processor sub-systems using the omap_device
API which are currently supplied as platform data ops. Use pdata
quirks to maintain the functionality as the OMAP iommu driver
gets converted to use DT nodes, until the reset portions are
decoupled from omap_hwmod/omap_device into a separate reset
driver.
This patch adds the pdata quirks for the reset management of
iommus within the DSP (OMAP3 & OMAP4) and IPU subsystems (OMAP4).
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The IOMMU DT adaptation support uses the device name instead
of an iommu object name. Fixup the ISP device archdata MMU
name at runtime if using DT-boot. This allows the OMAP3 camera
to be functional in both legacy and DT boots. The iommu object
names should eventually vanish when all the IOMMU users have
been converted to DT nodes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The IVA MMU is not functional when used through the hwmod and
omap_device layers. Add fixes to clockdomain and hwmod data
to have it functional. The hwmod changes are needed to enable
the clock, and the SWSUP change is needed to wakeup the domain
because the power domain is programmed to be in RET, and there
is no automatic power domain switching to ON.
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
CONFIG_OMAP_IOMMU_IVA2 was defined originally to avoid conflicting
usage by tidspbridge and other iommu users. The same can be achieved
by marking the DT node disabled, so remove this obsolete flag and
the corresponding hwmod data can be enabled.
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
[s-anna@ti.com: revise commit log]
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Touchscreen support for at91_adc has been introduced so we can get rid of
atmel_tsadcc.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
atmel,at91sam9rl-udc is a USB gadget, it has no means to control vbus.
atmel,vbus-gpio is in fact used to detect the presence of vbus.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
[nicolas.ferre@atmel.com: modify the commit message]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
in the dts files.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQIcBAABAgAGBQJTGgeNAAoJEBvUPslcq6VzbUUQAIUaGol4O4YDhJn/94ArIKlE
+IoIfsIGaVsP2e+Dzgqtjj7PXXmEPrSy3iQEVFXwshqt5eB2I33uSJXQxSIXwxTi
i35sCFmF4wLmznh4uJZvj2/0hpimJp5mBRQpnEnueMik+Tg8puRnAsnC/7us3eVT
pDkzKmNhibZVoz38SNSVC9+Qmv670RtOXEFIB01yfeXtSy57BQytRgHZqA893bUw
q94+bWHusHcAKsUNsijXkDPrBEvyAgqyzz+ynVN9zJ64LaT7MDym8LUN5ud1z5Wd
Q1hlo38wPDf23ipJxxI2p0HZ1PQ9oXPbrDNw8PuExoFBqJpSpMpZqRHxpYOrw/0U
uReQ9opGh+pbCm/eJYEp8CQ22nX2Pswdquozczjp6AICL4lyjYlH5o/3pIaL7cIE
RJ/lxL1OaFtOzQILHgQtzWuFXvs6xHGfHUCSHbJzwBp5+11p61vV2bcL0QqFHw5q
Io0ookcnJaideiXrxWdfVSmNQz8Rc5VEKqkCh43S06SufaMmfbnbpDP5ZO27zofz
HuXV6SRlAZbshtBEQsUnx8u9icLW7V23Hj9D+/13bFxn8Sk+63/UEvoCfiPkeZXj
hKdk3XZRrwzKVlugFGqqdlrnmc8ZKXwYcKhYBsPtdm+cGA1YphPRQGAgVa9ctWdG
c208VrT83bnwpc5Te10I
=g3T0
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.15/dt-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Merge "omap device tree changes for v3.15, part 2" from Tony Lindgren:
Part two of omap device tree changes enabling driver features
in the dts files.
* tag 'omap-for-v3.15/dt-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x-evmsk: enable dual_emac mode
ARM: dts: DRA7: Add device nodes for ABB
ARM: dts: OMAP4: Add device nodes for ABB
ARM: dts: OMAP36xx: Add device node for ABB
ARM: dts: am43x-epos-evm: add SD card hotplug support
ARM: dts: am335x-evm: add SD card hotplug support
ARM: dts: am437x gp-evm: add sd card dt nodes
ARM: dts: omap5: added dt properties to adapt to the new phy framwork
ARM: OMAP2+: Use pdata quirks for wl12xx on the AM335x EV-MSK
ARM: dts: Update echi-omap DT binding example usage
ARM: dts: Get rid of incompatible ids for hci-omap USB host nodes
ARM: OMAP2+: Remove legacy_init_ehci_clk()
ARM: dts: Add support for OMAP4 Gumstix DuoVero/Parlor
Signed-off-by: Olof Johansson <olof@lixom.net>
A variety of features are added to the bcm2835 device trees:
- ARM PMU, for perf_event
- DMA controller
- I2S controller
A few cleanups are applied to the DTs too.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJTGTGiAAoJEJuNpwkmVCGcRWQP/1oe3/PF6pEZgCy5887uCy9z
RUj8eSLQk4QelyFSlDJ0ChvgCez6bb72Lw5Tm9gh2CNX3vMnTAWqLlLFuYlXgMjh
agKthe1ZG2uHlRfVdVgQlRW1hivdCF+5DzvnAJ0pUkhaWzG9L9mtPVXozpFEsWur
leu9E5JfWSnc6YW+iGtyxQ3l5SmWMFv6D+nChWlGx5jz40g/kieiI0toiiIIu/mb
OtIzucUtQqmINPzVIktpe2m8qwdXPL6W4ktH9Y5/Cg8AGI/WCHWRCS1VZZ8uzkHs
/yZbs5cK0pnJKbXnJqUrTe+zuaxW7xyp3WonZrIRN72cz5qvi7LAneEOZcYJ3cqz
r19yEahzmZrhTdQZKC1CuaEDk9e6GckP6FUbUv3eGcwGoQU0I942JpVgGEVQ5P1Y
NGTDQU9OawkHuxlZl9hOLZkunAzY0GHbR73AZ2SqYXyzN5t4kCURF0RyOq8J9nL0
A58XpmuWOpeOuBuqCKxgVEd+5c3BYDE1oiSWwSHCcGotWb7zvyIgqGp+JbEE+KFf
PHqUhv8g1FIGpwYK/M4dP8oqClaFKXzo44QbrojlLOHCu/zaEXnNu4fDX02hfit/
W0d6YymesUQGBk0cxmxC/3CfJN/Vpc8BtIhW0Yxdhi3U9sLDyWgl0TZEETD1ARk6
m6BIR2gbuqINemEGy+0V
=pjrN
-----END PGP SIGNATURE-----
Merge tag 'bcm2835-for-3.15-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/dt
Merge "ARM: bcm2835: DT changes for 3.15" from Stephen Warren:
A variety of features are added to the bcm2835 device trees:
- ARM PMU, for perf_event
- DMA controller
- I2S controller
A few cleanups are applied to the DTs too.
* tag 'bcm2835-for-3.15-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: fix clock DT node names
ARM: bcm2835: node name unit address cleanup
ARM: bcm2835: fix DT node sort order
ARM: bcm2835: add I2S driver to device tree
ARM: bcm2835: add dmaengine driver to device tree
ARM: bcm2835: perf_event support for Raspberry-Pi
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds IRB support to STiH416 platforms.
Tested on B2000 and B2020 development board
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds IRB support to STiH415 platforms.
Tested on B2000 and B2020 development boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH416 SOC, which has two ethernet
snps,dwmac controllers version 3.710. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds support to STiH415 SOC, which has two ethernet
snps,dwmac controllers version 3.610. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds soft reset controller support for STiH415 and adds new
softreset lines required for other device tree nodes in the header file.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds a reset controller node to the SOC device tree and also
adds new header files with reset lines required for other device tree
nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds soft reset controller support for STiH415 and adds new
softreset lines required for other device tree nodes in the header file.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
This patch adds a reset controller node to the SOC device tree and also
adds new header files with reset lines required for other device tree
nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Add the "atmel,nand-has-dma" property to NAND node for SoC that
can use the DMA to perform NAND accesses.
Use of this property was added in 1b7192658a08f70df0f290634fd7cd2ecb629fc9
(mtd: atmel_nand: add a new dt binding item for nand dma support).
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris BREZILLON <b.brezillon@overkiz.com>
- Add USB, GPMI and SATA support for imx6q-phytec board
- Update imx6sl-evk board support regarding PFUZE100, audio and
LED etc.
- Minor updates on a few imx6qdl boards
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJTFojxAAoJEFBXWFqHsHzOYxQH/AxyYbMJbxYT9ml0cu4Y6Ond
wXlEkzTIzKQQWEH3ikfDvY4oD2DjLo4S884rXXOaGTXTLoc3uwp2x4Uav2PGCI8h
zMmCjTV8rPMAEtwLOADCN/Ku9MQgyW0/4rR2ZCm8ZGsYkyXcZueAkpK3EwrpPRJw
oJk+SUEWCE4Hbw26p2scTzw0Bn3AL/MEjdZ061qi5Tv0AJF7TCRv9OvRUNePqdgA
LKtlFGHPDAVNLXSy/ChR8PXcBI5h+zF+ZwiQupen29RQ67BvUKEXtBdnM/SNTp2z
yqqsurAnypAUs7yOkhAqHsu+EPOuOmhuepgU6tmOhY791Z5xA+no4h6e7inEUsw=
=6Hku
-----END PGP SIGNATURE-----
Merge tag 'imx6-dt-3.15-2' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
i.MX6 device tree changes for 3.15, take 2 from Shawn Guo:
- Add USB, GPMI and SATA support for imx6q-phytec board
- Update imx6sl-evk board support regarding PFUZE100, audio and
LED etc.
- Minor updates on a few imx6qdl boards
* tag 'imx6-dt-3.15-2' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: dts: imx6q-phytec: Added SATA Support
ARM: dts: imx6q-phytec: Added GPMI-NAND Support
ARM: dts: imx6q-phytec: Added USB_HOST Support
ARM: dts: imx6q-phytec: Added USB_OTG Support
ARM: dts: imx6sl-evk: Keep VGEN1 regulator always enabled
ARM: dts: imx6qdl-sabreauto: Support debug LED
ARM: dts: imx6q: add 852MHz setpoint for CPU freq
ARM: dts: imx6qdl-wandboard: use GPIO_6 for FEC interrupt
ARM: dts: imx6sl-evk: Add debug LED support
ARM: dts: imx6qdl-sabreauto: Add PFUZE100 support
ARM: dts: imx6sl-evk: Add audio support
ARM: dts: imx6sl-evk: Add PFUZE100 support
ARM: dts: imx6qdl-sabresd: correct gpio key's active state
Signed-off-by: Olof Johansson <olof@lixom.net>
- Rename SSP/SPI clocks to the name found in the hardware
reference manual. (Also includes a rename in the U300
device tree file.)
- Delete dead non-DT code.
- Drop now completely unused GPIO definition header file.
- Delete all hardcoded IRQ number assignments. This hits
MFD a bit so the patch has been ACKed by Lee Jones from
the MFD side.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJTFSanAAoJEEEQszewGV1zGzUP/0Llq11lEo4wCaBKnRQL2EvE
bE3oiRKq0qfQko0m1iui1jUO/sGHeaxUuNcF6rXo/sD6Zcd16mLs8ENW5BWmo4AV
wb61RycBspM1bJHVXSWu07MPNpcvRdYAquvQkrWBAD4MIbYX4RY6lE/lIXjP8v4x
l1g92MOCiIcOxwc1E7SeXk4H5/wI3DEzdCiOwyxueQlXUEc+OiKN4A3IDCRDA0/S
yqN/Gjsj8rc8RG7YPIqBm4E4Msju7Jy9WE+hebrOZZ9rWfHpw7WMTdHfRR1KhzRm
tM8Hm5I/doFCqQ7RcczueIogk9ogkQKuvg0vSdmXKcnfBuOkXjowedEIVz+gmTGn
jd0TbaY3z5pzGMYMTFmOfRuSeq2O/K6CsXaPvfs0ugiFDKU2lWzF3tv/1boO/GYc
tIzVB93l5HRIQlfQWFHDavXakxVuRVvv3yfQD+q1F7QP/CbNYQ1scEZio5XfQtDs
YVFSqazzgISDgUaVVukzoWb8lPTI65/F/Rn5kLTEoPMEVSe0yGGoxTPK/TYfUdOn
XCytmyTBMlaDvyn+GQrM6FZXXdCiTs2GJrstkcR7tioPWC+gyvIOXWu212MbLod2
bjc/l/IK4KmtwYvMChk2j313mFiDqTwi1DTwhejgGP4DT/nC/cwqKyvG3YW2nq0G
rFDyua9CmtRCuAgxBBIU
=pCAM
-----END PGP SIGNATURE-----
Merge tag 'ux500-dt-v3.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt
A set of device tree-related cleanups for the ux500 platform from Linus
Walleij:
- Rename SSP/SPI clocks to the name found in the hardware
reference manual. (Also includes a rename in the U300
device tree file.)
- Delete dead non-DT code.
- Drop now completely unused GPIO definition header file.
- Delete all hardcoded IRQ number assignments. This hits
MFD a bit so the patch has been ACKed by Lee Jones from
the MFD side.
* tag 'ux500-dt-v3.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
mfd: dbx500/abx500: root out hardcoded IRQ assignments
ARM: ux500: drop a chunk of GPIO definitions
ARM: ux500: skip GIC CPU and dist address checks
ARM: ux500: delete pointless DT config option
ARM: u300: switch SSP/SPI clock name to "SSPCLK"
ARM: ux500: switch SSP/SPI clock name to "SSPCLK"
Signed-off-by: Olof Johansson <olof@lixom.net>
- use macros instead of hard coded numbers for clock bindings
NOTE: this is based on v3.15-next/dt-samsung
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJTE9QWAAoJEA0Cl+kVi2xqDBAQAJORPoEBQOs+Y2vHughs16jg
48uG6ttIFcjo9HRe0DVpEBE4gyQzIUGOgU/8ebU29kA2Ce0calTQZDZZ4YQZ1LXL
zc1MACqS2LBKoeFFCpyq61ghtNWjTyoQCgkQi6C/GNUv36uEuIAUPD5Cj+j5eUfS
M6bHImxE0sHFxYzZPQ3BGO0gN7IoPEGYrXJmgD5LbswBgYP3qbFckr/spGzKb0Yt
LyLTiZzb03l9C8lpaRkzA6AzAUJSqH2ialD7cEIVgxG1/Zmx0p2fW0ORpXWoU4Tp
vM7akP4ZkdDdW5fUZOVklzjxnBG3pKOXivOeZ28K66vS3u5RRJYHd7gq4/d77JUe
Jzz6s3jmr5Rk5UVtqrPNqu7SRz8RR9j5MBJ2gKDJK4GVelGqk8KgWdfAF/BGzGdj
FbZMh3TzPMJxrcLTNDDaBrawg/mxQifV2ixV3hHFUtjw6Bbocxo5NDmG2sol8zQU
XI7IlFzTQzqkb5KLYfPS3OGfBAvLUXfe9XT/XJkrSVYHXj7DJEonbZlTrxp35HYA
0bFacDXMMqwqqaGjMsAbIslq0QUNBU97ztmmwInYfrBwah1nO3QxDhfATRF3VrHa
264vnh1l97uWjN/iwTXMeZC6+ng2KqmQvrIbXc4d02buVRcnDIY+v5M11CY1AUFt
Sz112ddWErQHi2MQoEJ0
=4qfh
-----END PGP SIGNATURE-----
Merge tag 'exynos-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
Samsung exynos clock related DT updates for v3.15 from Kukjim Kim:
- use macros instead of hard coded numbers for clock bindings
NOTE: this is based on v3.15-next/dt-samsung
* tag 'exynos-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: use macros in clock bindings for exynos5440
ARM: dts: use macros in clock bindings for exynos5420
ARM: dts: use macros in clock bindings for exynos5250
ARM: dts: use macros in clock bindings for exynos4
For exynos4412
- update vdd_arm voltage range for odroidx board
For exynos5250
- add PMU sysreg node and update watchdog node
- re-organize RTC status
- add max77686 pmic node for smdk5250
For exynos5420
- add PMU sysreg, i2s, adma and watchdog nodes
- re-organize RTC status
- add fixed voltage regulators and regulator nodes
for smdk5420
- add PMIC, GPIO based wake up key and vmmc-supply
support for arndale-octa board
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJTE9IiAAoJEA0Cl+kVi2xqOooQAIzTTXaGBpwM65jyEHL2/lgL
AL9F/Q1FN8oeBTwomnfDOqbiNQh4bufXm7suCbp/whugnL2BzXghDT9wij0vcpH4
DjXtbQRa7/dKcnncFHWUAaKnMGQZCJi0Wk1TRNbeJPDmOt12hghp73uAvUtrCxlF
K5s3fCRc7ZapmHztgbu2vPvPzXGjLT68l4ccS1whqZIgsFZHQZDcUVRnugbc43yf
JzrANbONbFROiuUFVWNx6nJ/n0AscMxpisQg66ngdlmi0q1CWqNK78kKwc56sw2L
XN7m92im6D2HOhIsGULZQqy82EWtpsdW1z7zuuau9YMiG5qMVfZtPaHeMGwEg1W6
/Zxd0NdcIopS73hC+zf75girzGmR7gIorlAOEVNM6DZcXtrCNkiEYx3/E+XgIP7r
Vmebgm9KvQaYEqmfFvK1PKN/T1ySeCBkNiqrvjWaMEOtF9pL6WqE1aEBD78dPg/C
Gjt9tYpiDtvxNzqwg7YQyYYmaGbKwMRR3ARd5qd3oFubu8pJLLNZvbQUCJzy0buD
bgfofA/4c/p2QNLluPdM51XuiXMXG/4ienKbPjKEE5XWmXeZY8OdtWvNXw+rAVXX
2Xa7KPclIOvKxsa/DPb2n0FJg8izx/Ns5l3ANqzrXv2q+ckldy7wZ4Sxu1L+qYWM
l+XIdU4I8c/K3QDDPsND
=eUF9
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
Samsung DT updates for v3.15 from Kukjin Kim:
For exynos4412
- update vdd_arm voltage range for odroidx board
For exynos5250
- add PMU sysreg node and update watchdog node
- re-organize RTC status
- add max77686 pmic node for smdk5250
For exynos5420
- add PMU sysreg, i2s, adma and watchdog nodes
- re-organize RTC status
- add fixed voltage regulators and regulator nodes
for smdk5420
- add PMIC, GPIO based wake up key and vmmc-supply
support for arndale-octa board
* tag 'samsung-dt' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Add vmmc-supply to MMC on arndale-octa board
ARM: dts: Add wake up key to arndale-octa board
ARM: dts: Add PMIC support to arndale-octa board
ARM: dts: Add fixed voltage regulators to smdk5420
ARM: dts: Add I2S nodes to exynos5420
ARM: dts: Add ADMA node to exynos5420
ARM: dts: Re-organize RTC status for exynos5250
ARM: dts: Re-organize RTC status for exynos5420
ARM: dts: Add regulator entries to smdk5420
ARM: dts: add max77686 pmic node for smdk5250
ARM: dts: update vdd_arm voltage range for exynos4412 based boards
ARM: dts: update watchdog device nodes for exynos5250 and exynos5420
ARM: dts: Add pmu sysreg node to exynos5250 and exynos5420
Signed-off-by: Olof Johansson <olof@lixom.net>
The A31 Colombus board has 3 I2C controllers that should be usable. However,
the first one is not working for some reason on the hardware I have been able
to test it on, while it should really be the same controller. Enable the i2c1
and i2c2 busses, and mark i2c0 as in failure in the DT.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The i2c controllers have a few muxing options on the A31. Enable the
ones found in the A31 Colombus board.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A31 has 4 I2C controllers that are the same than the one in the
other Allwinner SoCs, except for the fact that they are asserted in
reset by the reset unit.
Add these i2c controllers to the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Marvell Dove's pinctrl does require some PMU regs for muxing PMU
functions to MPP pins. Recently, a discussion started about consolidating
Power Management Unit (PMU) into a single DT node. As we don't want
anymore DT ABI in the way, drop the corresponding reg property from
pinctrl node now. The driver will derive the registers from existing
reg properties.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 385 RD board is the reference design board from Marvell
for the Armada 385 SoC. This commit adds a Device Tree description for
this board, which enables the following features:
* Network interfaces
* I2C bus
* Serial port
* SPI bus, with a SPI flash
* PCIe interface
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
On Armada 385 DB, while the "rgmii" PHY connection mode works fine
with the generic PHY driver, it fails to work when the Marvell PHY
driver is enabled in the kernel configuration, due to a finer handling
of the PHY configuration. This is due to the fact that the phy
connection mode should instead be "rgmii-id", i.e with the TX/RX delay
mechanisms enabled.
This fixes the network operation on Armada 385 DB with
CONFIG_MARVELL_PHY=y. Without this patch and this option enabled, one
would only get messages such as:
mvneta f1070000.ethernet eth1: bad rx status 0cc10000 (crc error), size=70
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Since the Armada XP Matrix board has 4 GB of RAM and not 2 GB, we
update the Device Tree to take into account the correct amount of
memory. As noted in the new comment, the last 256 MB of RAM are in
fact not usable, due to the overlap with the MBus Window address
range.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Marvell has now provided bootloaders that are Device Tree capable for
the Armada XP GP board, and that also remap the internal register base
address to 0xf1000000. In addition, the bootloader now sets the MBus
Window base address to 0xf0000000, which allows to use much more RAM
in the last GB of RAM before the 4 GB limit (the entire space from
0xC0000000 to 0xFFFFFFFF was not usable due to being used for I/O, not
only the space from 0xF0000000 to 0xFFFFFFFF is used for I/O).
Therefore this commit:
* Updates the memory->reg Device Tree property with the fact that in
the first bank of RAM, memory up to 0xf0000000 can be used.
* Updates the soc->ranges Device Tree property with the fact that the
internal registers are now mapped at 0xf1000000.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Marvell has now provided bootloaders that are Device Tree capable for
the Armada XP DB board, and that also remap the internal register base
address to 0xf1000000. In addition, the bootloader now sets the MBus
Window base address to 0xf0000000, but on this board, this change
doesn't make much difference since the board is by default equipped
with 2 GB of RAM.
Therefore this commit updates the soc->ranges Device Tree property
with the fact that the internal registers are now mapped at
0xf1000000.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The latest Marvell bootloaders for various boards change the MBus
Window base address from 0xC0000000 to 0xF0000000, in order to make
more RAM in the first 4 GB actually usable by the kernel (RAM that is
covered by the MBus window is "shadowed" and therefore not usable).
However, our default PCIe memory and I/O apertures where sitting at
0xe0000000 (for memory) and 0xe8000000 (for I/O), which will now be
outside of the MBus Window range on those platforms. To make things
work, we have to ensure those apertures use addresses in the
0xF0000000 -> 0xFFFFFFFF range.
Of course this change of the MBus Window base address from 0xC0000000
to 0xF0000000 also comes with a change of the internal register base
address from 0xD0000000 to 0xF1000000.
We have therefore designed the following memory map:
* 0xF0000000 -> 0xF1000000: 16 MB, used for NOR flashes on Armada XP
GP and Armada XP DB.
* 0xF1000000 -> 0xF1100000: 1 MB, used for internal registers.
* 0xF8000000 -> 0xFFE00000: 126 MB, used for PCIe memory.
* 0xFFE00000 -> 0xFFF00000: 1 MB, used for PCIe I/O.
* 0xFFF00000 -> 0xFFFFFFFF: 1 MB, used for the BootROM mapping
There is one exception to this layout: the Armada XP OpenBlocks, which
has a 128 MB NOR flash, mapped from 0xF0000000 to 0xF8000000. This
does not conflict with the current change for the PCIe I/O and memory
apertures, and continues to work because on Armada XP OpenBlocks, the
bootloader is an old one, and continues to have internal registers
mapped at 0xD0000000.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Those are defined by the common PCI binding.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124 can support 4GB of RAM. With that much RAM (plus some memory-
mapped IO peripherals), more than 32-bits of physical address space is
required. Hence, convert all Tegra124 DTs to use 2 DT cells for address
space.
(I think this was suggested by Olof Johansson, but I'm not 100% sure)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
EVM board provides two Ethernet ports, this patch sets them into
dual_emac mode to provide two independent network interfaces.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
