57473 Commits

Author SHA1 Message Date
Stefan Agner
fe09d9c641 ARM: 8852/1: uaccess: use unified assembler language syntax
Convert the conditional infix to a postfix to make sure this inline
assembly is unified syntax. Since gcc assumes non-unified syntax
when emitting ARM instructions, make sure to define the syntax as
unified.

This allows to use LLVM's integrated assembler.

Additionally, for GCC ".syntax unified" for inline assembly.
When compiling non-Thumb2 GCC always emits a ".syntax divided"
at the beginning of the inline assembly which makes the
assembler fail. Since GCC 5 there is the -masm-syntax-unified
GCC option which make GCC assume unified syntax asm and hence
emits ".syntax unified" even in ARM mode. However, the option
is broken since GCC version 6 (see GCC PR88648 [1]). Work
around by adding ".syntax unified" as part of the inline
assembly.

[0] https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html#index-masm-syntax-unified
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88648

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:20:52 +01:00
Stefan Agner
a6c9e96bf8 ARM: 8851/1: add TUSERCOND() macro for conditional postfix
Unified assembly syntax requires conditionals to be postfixes.
TUSER() currently only takes a single argument which then gets
appended t (with translation) on every instruction.

This fixes a build error when using LLVM's integrated assembler:
  In file included from kernel/futex.c:72:
  ./arch/arm/include/asm/futex.h:116:3: error: invalid instruction, did you mean: strt?
          "2:     " TUSER(streq) "        %3, [%4]n"
           ^
  <inline asm>:5:4: note: instantiated into assembly here
  2:      streqt  r2, [r4]
          ^~~~~~

Additionally, for GCC ".syntax unified" for inline assembly.
When compiling non-Thumb2 GCC always emits a ".syntax divided"
at the beginning of the inline assembly which makes the
assembler fail. Since GCC 5 there is the -masm-syntax-unified
GCC option which make GCC assume unified syntax asm and hence
emits ".syntax unified" even in ARM mode. However, the option
is broken since GCC version 6 (see GCC PR88648 [1]). Work
around by adding ".syntax unified" as part of the inline
assembly.

[0] https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html#index-masm-syntax-unified
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88648

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:20:51 +01:00
Linus Walleij
1fae0ad1e2 ARM: dts: Add queue manager and NPE to the IXP4xx DTSI
The AHB queue manager and Network Processing Engines are
present on all IXP4xx SoCs, so we add them to the overarching
device tree include.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:16 +02:00
Linus Walleij
ecc133c6da soc: ixp4xx: qmgr: Pass resources
Instead of using hardcoded base address implicitly
obtained through <linux/io.h>, pass the physical base
for the QMGR block as a memory resource and remap
it in the driver.

Also pass the two IRQs as resources and obtain them
in the driver.

Use devm_* accessors and simplify the error path in the
process. Drop memory region request as this is done by
the devm_ioremap* functions.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:16 +02:00
Linus Walleij
0b458d7b10 soc: ixp4xx: npe: Pass addresses as resources
Instead of using hardcoded base addresses implicitly
obtained through <linux/io.h>, pass the physical base
for the three NPE blocks as memory resources and remap
these in the driver.

Drop the memory request region business, this will
anyways be done by devm_* remapping functions.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij
81bca32fcc ARM: ixp4xx: Turn the QMGR into a platform device
Instead of registering everything related to the QMGR
unconditionally in the module_init() call (which will
never work with multiplatform) create a platform device
and probe the QMGR like any other device.

Put the device second in the list of devices added for
the platform so it is there when the dependent network
and crypto drivers probe later on.

This probe() path will not be taken unconditionally on
device tree boots, so remove the DT guard.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij
bc4d7eafb7 ARM: ixp4xx: Turn the NPE into a platform device
Instead of registering everything related to the NPE
unconditionally in the module_init() call (which will
never work with multiplatform) create a platform device
and probe the NPE like any other device.

Put the device first in the list of devices added for
the platform so it is there when the dependent network
and crypto drivers probe later on.

This probe() path will not be taken unconditionally on
device tree boots, so remove the DT guard.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij
4af20dc583 ARM: ixp4xx: Move IXP4xx QMGR and NPE headers
This moves the IXP4xx Queue Manager and Network Processing
Engine headers out of the <mack/*> include path as that is
incompatible with multiplatform.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij
fcf2d8978c ARM: ixp4xx: Move NPE and QMGR to drivers/soc
The Network Processing Engine and Queue Manager are
versatile firmware components used by several IXP4xx
drivers.

Drivers are relying on getting access to these components
using <mach/*> headers which does not work with
multiplatform. We need to find a better place for the
drivers to live.

Let's first move them to drivers/soc and the start to
refactor a bit by passing resources and moving headers.

This patch introduce static IRQ assignments but that
will be fixed by later patches in this series.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij
b9a35d705a ARM: dts: Add some initial IXP4xx device trees
This adds a device tree for the IXP4xx-based Linksys
NSLU2 and Gateworks GW2358 which encompass the Gateworks
Cambria family.

These will be the first IXP4xx device tree platforms.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij
9540724ca2 ARM: ixp4xx: Add device tree boot support
This adds a minimal support for booting IXP4xx systems
from device tree.

We have to add hacks to the QMGR, NPE and notably also
ethernet and watchdog drivers so that they don't crash
the platform: these drivers are unconditionally starting
to grab regions of statically remapped IO space with no
concern of the device model or other platforms.

We will go in and properly fix these drivers as we go
along but for now this hack gets us to a place where we
can start working on proper device tree support for these
platforms.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij
65af666713 ARM: ixp4xx: Switch to use new timer driver
This augments the IXP4xx to select and use the new
timer driver in drivers/clocksource and removes the old
code in the machine.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:14 +02:00
Linus Walleij
55ec465e73 ARM: ixp4xx: Switch to use new IRQ+GPIO drivers
This deletes the old irq+gpiochip combo from the IXP4xx
machine and switches it over to use the new drivers merged
in respective subsystem.

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:13 +02:00
Andrey Smirnov
4171797ff7 ARM: dts: imx7s: Specify #io-channel-cells in ADC nodes
Specify #io-channel-cells in ADC nodes. Needed to be able to reference
them by phandle.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-23 09:48:26 +08:00
Jens Axboe
5c61ee2cd5 Linux 5.1-rc6
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Merge tag 'v5.1-rc6' into for-5.2/block

Pull in v5.1-rc6 to resolve two conflicts. One is in BFQ, in just a
comment, and is trivial. The other one is a conflict due to a later fix
in the bio multi-page work, and needs a bit more care.

* tag 'v5.1-rc6': (770 commits)
  Linux 5.1-rc6
  block: make sure that bvec length can't be overflow
  block: kill all_q_node in request_queue
  x86/cpu/intel: Lower the "ENERGY_PERF_BIAS: Set to normal" message's log priority
  coredump: fix race condition between mmget_not_zero()/get_task_mm() and core dumping
  mm/kmemleak.c: fix unused-function warning
  init: initialize jump labels before command line option parsing
  kernel/watchdog_hld.c: hard lockup message should end with a newline
  kcov: improve CONFIG_ARCH_HAS_KCOV help text
  mm: fix inactive list balancing between NUMA nodes and cgroups
  mm/hotplug: treat CMA pages as unmovable
  proc: fixup proc-pid-vm test
  proc: fix map_files test on F29
  mm/vmstat.c: fix /proc/vmstat format for CONFIG_DEBUG_TLBFLUSH=y CONFIG_SMP=n
  mm/memory_hotplug: do not unlock after failing to take the device_hotplug_lock
  mm: swapoff: shmem_unuse() stop eviction without igrab()
  mm: swapoff: take notice of completion sooner
  mm: swapoff: remove too limiting SWAP_UNUSE_MAX_TRIES
  mm: swapoff: shmem_find_swap_entries() filter out other types
  slab: store tagged freelist for off-slab slabmgmt
  ...

Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-04-22 09:47:36 -06:00
Andrey Smirnov
2ea5c9b28f ARM: dts: vf610-zii-dev-rev-b: Specify CS as GPIO_ACTIVE_LOW in spi0
Specify CS as GPIO_ACTIVE_LOW in spi0 to fix the following warning:

m25p128@0 enforce active low on chipselect handle

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22 09:16:15 +08:00
Andrey Smirnov
1437626ec4 ARM: dts: vf610-zii-dev: Mark i2c0 SCL as GPIO_OPEN_DRAIN
Mark i2c0 SCL as GPIO_OPEN_DRAIN to fix the following warning:

gpio-36 (scl): enforced open drain please flag it properly in DT/ACPI DSDT/board file

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22 09:15:59 +08:00
Andrey Smirnov
69ab5392f5 ARM: dts: Add support for ZII i.MX7 RPU2 board
Add support for ZII's i.MX7 based Remote Peripheral Unit 2 (RPU2)
board.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22 09:03:35 +08:00
Bruno Thomsen
5ea0c200bd ARM: dts: bugfix tqma7 soft reset issue
Running reboot command on the TQMa7 board would just hang infinite
at the end of the system shutdown process.

Handling of i.MX7 errata e10574:
Watchdog: A watchdog timeout or software trigger will not reset the SOC.

Moved pinctrl from common mba7 to common tqma7 dtsi as it improves
readability of errata handling. Most integrators of this SoM will
likely use the development board as inspiration for handling this
SoC issue.

Signed-off-by: Bruno Thomsen <bruno.thomsen@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22 08:51:49 +08:00
Chris Packham
7971cc408d ARM: mvebu: kirkwood: remove error message when retrieving mac address
Kirkwood has always had the ability to retrieve the local-mac-address
from the hardware (usually this was configured by the bootloader). This
is particularly useful when dealing with a legacy non-DT aware
bootloader.

The "error" message just indicated that the board used an old bootloader
and in many cases users can't do anything about this. The message
probably should have been pr_info() to inform the user that the kernel
has been helpful but rather than than let's remove it entirely to make
the kernel less noisy.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-21 19:01:41 +02:00
Chris Packham
71f2b9957d ARM: dts: armada-38x: add interrupts for watchdog
The first interrupt is for the regular watchdog timeout. Normally the
RSTOUT line will trigger a reset before this interrupt fires but on
systems with a non-standard reset it may still trigger.

The second interrupt is for a timer1 which is used as a pre-timeout for
the watchdog.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-21 18:26:20 +02:00
Marek Vasut
716be61d18 ARM: dts: imx53: Add Menlosystems M53 board
Add device tree for the Menlosystems board based on i.MX53 M53 SoM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-21 16:02:30 +08:00
Marek Vasut
6143613a84 ARM: dts: imx53: Rename M53 SoM touchscreen node
Rename the touchscreen node to match contemporary design.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-21 16:02:13 +08:00
Vladimir Oltean
c7861adbe3 ARM: dts: ls1021: Fix SGMII PCS link remaining down after PHY disconnect
Each eTSEC MAC has its own TBI (SGMII) PCS and private MDIO bus.
But due to a DTS oversight, both SGMII-compatible MACs of the LS1021 SoC
are pointing towards the same internal PCS. Therefore nobody is
controlling the internal PCS of eTSEC0.

Upon initial ndo_open, the SGMII link is ok by virtue of U-boot
initialization. But upon an ifdown/ifup sequence, the code path from
ndo_open -> init_phy -> gfar_configure_serdes does not get executed for
the PCS of eTSEC0 (and is executed twice for MAC eTSEC1). So the SGMII
link remains down for eTSEC0. On the LS1021A-TWR board, to signal this
failure condition, the PHY driver keeps printing
'803x_aneg_done: SGMII link is not ok'.

Also, it changes compatible of mdio0 to "fsl,etsec2-mdio" to match
mdio1 device.

Fixes: 055223d4d22d ("ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR")
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-21 15:51:28 +08:00
Vladimir Zapolskiy
d5a71e4646 ARM: dts: lpc32xx: use SPDX license identifier
Replace GPLv2+ header with the SPDX identifier.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 23:57:12 +03:00
Vladimir Zapolskiy
cea8623867 ARM: dts: lpc32xx: add address and size cell values to SPI controller nodes
All 4 SPI controllers on NXP LPC32xx SoC support SPI slaves discerning them
by one cell address value, set it as default to avoid duplication in board
device tree files.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 23:57:04 +03:00
Vladimir Zapolskiy
4c546175db ARM: dts: lpc32xx: disable MAC controller by default
NXP LPC3220 and LPC3230 SoCs do NOT contain a MAC controller, so,
since for now there is just one dtsi file for all variants of
NXP LPC32xx SoCs, it is reasonable to disable the controller
by default and enable it in device tree files of particular boards.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 23:56:57 +03:00
Vladimir Zapolskiy
903fa2ab79 ARM: dts: lpc32xx: disable I2S controllers by default
The I2S controllers found on NXP LPC32xx SoCs are not yet in
use by any boards supported in upstream, disable the controllers
by default.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 23:56:48 +03:00
Vladimir Zapolskiy
37917ce5b4 ARM: dts: lpc32xx: change hexadecimal values to lower case
This is a non-functional change, all inconsistent hexadecimal values
found in the file are now fixed.

Taking a chance to interfere into some non-functional change I add
my copyright notice for work done during the last few years.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 23:56:40 +03:00
Vladimir Zapolskiy
e861cfbed0 ARM: lpc32xx: use SPDX license identifier
Replace GPLv2+ header with the SPDX identifier.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 22:59:30 +03:00
Vladimir Zapolskiy
bbf553c6bb ARM: lpc32xx: remove platform data of SSP0 and SSP1 controllers
Both controllers are described in lpc32xx.dtsi and there is no any
specific platform data added in the platform file.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 22:59:23 +03:00
Vladimir Zapolskiy
a1e65c28f6 ARM: lpc32xx: remove redundant included headers
While the majority of platform data was moved to device tree description
the list of included header files remained untouched, the change cleans
it up to an irreducible and observable subset.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 22:59:16 +03:00
Alexandre Belloni
a93fb4f407 ARM: lpc32xx: stop overwriting TEST_CLK_SEL
While the UDA1380 is described in some lpc3250 device trees, there is
currently no real user of that codec. Anyway, if the codec needs a clock,
it should take it explicitly.

lpc3250_machine_init is called for all the lpc32xx machines and some are
using test1_clk (for example to strobe an HW watchdog). Overwriting
TEST_CLK_SEL prevents booting those platforms.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 22:12:28 +03:00
Linus Walleij
dc8ef8cd3a ARM: ixp4xx: Convert to SPARSE_IRQ
This localizes the <mach/irqs.h> header to the mach-ixp4xx
directory, removes NR_IRQS and switches IXP4xx over to using
SPARSE_IRQ.

This is a prerequisite for DT support.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-19 20:37:44 +02:00
Linus Walleij
075df31aed ARM: ixp4xx: Pass IRQ resource to beeper
All IXP4xx devices except the beeper passes the IRQ as a
resource, augment the NSLU2 beeper to do the same.

This is a prerequisite for SPARSE_IRQ.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-19 20:37:40 +02:00
Linus Walleij
98ac0cc270 ARM: ixp4xx: Convert to MULTI_IRQ_HANDLER
This rewrites the IXP4xx to use MULTI_IRQ_HANDLER and
create an irqdomain for the irqchip in the platform. We
convert the timer to request the interrupt like any other
driver in the process.

We bump all IRQs to 16+offset to avoid using IRQ 0 and
set NR_IRQS to 512 (the default for most systems).
This conveniently fits with the first 16 IRQs being
pre-allocated when using SPARSE_IRQ.

This is a prerequisite for SPARSE_IRQ and DT boot.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-19 20:37:34 +02:00
David Howells
5dd50aaeb1
Make anon_inodes unconditional
Make the anon_inodes facility unconditional so that it can be used by core
VFS code and pidfd code.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
[christian@brauner.io: adapt commit message to mention pidfds]
Signed-off-by: Christian Brauner <christian@brauner.io>
2019-04-19 14:03:11 +02:00
Mathieu Desnoyers
bff9504bfc rseq: Clean up comments by reflecting removal of event counter
The "event counter" was removed from rseq before it was merged upstream.
However, a few comments in the source code still refer to it. Adapt the
comments to match reality.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Ben Maurer <bmaurer@fb.com>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Chris Lameter <cl@linux.com>
Cc: Dave Watson <davejwatson@fb.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Joel Fernandes <joelaf@google.com>
Cc: Josh Triplett <josh@joshtriplett.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Michael Kerrisk <mtk.manpages@gmail.com>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Paul Turner <pjt@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-api@vger.kernel.org
Link: http://lkml.kernel.org/r/20190305194755.2602-2-mathieu.desnoyers@efficios.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-04-19 12:39:31 +02:00
Dave Martin
92e68b2b1b KVM: arm/arm64: Clean up vcpu finalization function parameter naming
Currently, the internal vcpu finalization functions use a different
name ("what") for the feature parameter than the name ("feature")
used in the documentation.

To avoid future confusion, this patch converts everything to use
the name "feature" consistently.

No functional change.

Suggested-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-18 17:14:02 +01:00
Dave Martin
0323e027df KVM: arm: Make vcpu finalization stubs into inline functions
The vcpu finalization stubs kvm_arm_vcpu_finalize() and
kvm_arm_vcpu_is_finalized() are currently #defines for ARM, which
limits the type-checking that the compiler can do at runtime.

The only reason for them to be #defines was to avoid reliance on
the definition of struct kvm_vcpu, which is not available here due
to circular #include problems.  However, because these are stubs
containing no code, they don't need the definition of struct
kvm_vcpu after all; only a declaration is needed (which is
available already).

So in the interests of cleanliness, this patch converts them to
inline functions.

No functional change.

Suggested-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-18 17:14:01 +01:00
Dave Martin
a3be836df7 KVM: arm/arm64: Demote kvm_arm_init_arch_resources() to just set up SVE
The introduction of kvm_arm_init_arch_resources() looks like
premature factoring, since nothing else uses this hook yet and it
is not clear what will use it in the future.

For now, let's not pretend that this is a general thing:

This patch simply renames the function to kvm_arm_init_sve(),
retaining the arm stub version under the new name.

Suggested-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-18 17:14:01 +01:00
Chen-Yu Tsai
6e0c67e34f
ARM: dts: sun8i: a83t: Enable USB OTG controller on some boards
The Bananapi M3 and Cubietruck Plus both have USB OTG ports wired to the
SoC and PMIC in the same way, with the N_VBUSEN pin on the PMIC
controlling VBUS output, the PMIC's VBUS input for sensing VBUS, and
PH11 on the SoC for sensing the ID pin.

Enable OTG on both boards.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-18 17:49:43 +02:00
Quentin Schulz
6cb6cfd61e
ARM: dtsi: axp81x: add USB power supply node
The AXP813/818 has a VBUS power input. Add a device node for it, now
that we support it.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
[wens@csie.org: Add commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-18 17:49:43 +02:00
Eric Biggers
767f015ea0 crypto: arm/aes-neonbs - don't access already-freed walk.iv
If the user-provided IV needs to be aligned to the algorithm's
alignmask, then skcipher_walk_virt() copies the IV into a new aligned
buffer walk.iv.  But skcipher_walk_virt() can fail afterwards, and then
if the caller unconditionally accesses walk.iv, it's a use-after-free.

arm32 xts-aes-neonbs doesn't set an alignmask, so currently it isn't
affected by this despite unconditionally accessing walk.iv.  However
this is more subtle than desired, and it was actually broken prior to
the alignmask being removed by commit cc477bf64573 ("crypto: arm/aes -
replace bit-sliced OpenSSL NEON code").  Thus, update xts-aes-neonbs to
start checking the return value of skcipher_walk_virt().

Fixes: e4e7f10bfc40 ("ARM: add support for bit sliced AES using NEON instructions")
Cc: <stable@vger.kernel.org> # v3.13+
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-04-18 22:14:58 +08:00
Dmitry Osipenko
1078946b4b ARM: tegra: Add ACTMON support on Tegra30
Add support for ACTMON on Tegra30. This is used to monitor activity from
different components. Based on the collected statistics, the rate at
which the external memory needs to be clocked can be derived.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-18 11:37:46 +02:00
Dmitry Osipenko
a359de1b40 Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+"
Turned out that the actual bug was in the Memory Controller driver
that programmed shadowed registers without latching the new values
and then there was a bug on EMEM arbitration configuration calculation
that results in a wrong value being latched on resume from suspend.
The Memory Controller has been fixed properly now, hence the workaround
patch could be reverted safely.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-18 11:36:24 +02:00
Dmitry Osipenko
36841ba279 ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30
Tegra20/30 drivers do not handle the tick_broadcast_enter() error which
potentially could happen when CPU timer isn't permitted to be stopped.
Let's just move out the broadcasting to the CPUIDLE core by setting the
respective flag in the Tegra20/30 drivers. This patch doesn't fix any
problem because currently tick_broadcast_enter() could fail only on
ARM64, so consider this change as a minor cleanup.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-18 11:32:57 +02:00
Tudor Ambarus
c60fed1dfd ARM: at91: sama5: make ov2640 as a module
OV2640 is a detachable camera that we use to test the
Image Sensor Interface. Make it as a module, it will reduce
the kernel image size.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-04-18 10:55:40 +02:00
Miquel Raynal
72c5af0027 mtd: rawnand: Clarify Kconfig entry MTD_NAND
MTD_NAND is large and encloses much more than what the symbol is
actually used for: raw NAND. Clarify the symbol by naming it
MTD_RAW_NAND instead.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18 08:54:00 +02:00
Miquel Raynal
9bb94643b9 mtd: nand: Clarify Kconfig entry for software Hamming ECC entries
The software Hamming ECC correction implementation is referred as
MTD_NAND_ECC which is too generic. Rename it
MTD_NAND_ECC_SW_HAMMING. Also rename MTD_NAND_ECC_SMC which is an
SMC quirk in the Hamming implementation as
MTD_NAND_ECC_SW_HAMMING_SMC.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18 08:54:00 +02:00