linux

iv/linux

Fork 0

Commit Graph

Author	SHA1	Message	Date
Ilpo Järvinen	869b9eddf0	mfd: intel-m10-bmc: Add PMCI driver Add the mfd driver for the Platform Management Component Interface (PMCI) based interface of Intel MAX10 BMC controller. PMCI is a software-visible interface, connected to card BMC which provided the basic functionality of read/write BMC register. The access to the register is done indirectly via a hardware controller/bridge that handles read/write/clear commands and acknowledgments for the commands. Previously, intel-m10-bmc provided sysfs under /sys/bus/spi/devices/... which is generalized in this change because not all MAX10 BMC appear under SPI anymore. Co-developed-by: Tianfei zhang <tianfei.zhang@intel.com> Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com> Co-developed-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Co-developed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230116100845.6153-11-ilpo.jarvinen@linux.intel.com	2023-01-27 10:47:11 +00:00
Russ Weight	296f5568c6	mfd: intel-m10-bmc: Expose MAC address and count Create two sysfs entries for exposing the MAC address and count from the MAX10 BMC register space. The MAC address is the first in a sequential block of MAC addresses reserved for the FPGA card. The MAC count is the number of MAC addresses in the reserved block. Signed-off-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>	2021-02-08 13:54:25 +00:00
Xu Yilun	876611c493	mfd: intel-m10-bmc: Add Intel MAX 10 BMC chip support for Intel FPGA PAC This patch implements the basic functions of the BMC chip for some Intel FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the Intel MAX 10 CPLD. This BMC chip is connected to the FPGA by a SPI bus. To provide direct register access from the FPGA, the "SPI slave to Avalon Master Bridge" (spi-avmm) IP is integrated in the chip. It converts encoded streams of bytes from the host to the internal register read/write on the Avalon bus. So This driver uses the regmap-spi-avmm for register accessing. Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>	2020-09-30 17:46:21 +01:00

Author

SHA1

Message

Date

Ilpo Järvinen

869b9eddf0

mfd: intel-m10-bmc: Add PMCI driver

Add the mfd driver for the Platform Management Component Interface
(PMCI) based interface of Intel MAX10 BMC controller.

PMCI is a software-visible interface, connected to card BMC which
provided the basic functionality of read/write BMC register. The access
to the register is done indirectly via a hardware controller/bridge
that handles read/write/clear commands and acknowledgments for the
commands.

Previously, intel-m10-bmc provided sysfs under
/sys/bus/spi/devices/... which is generalized in this change because
not all MAX10 BMC appear under SPI anymore.

Co-developed-by: Tianfei zhang <tianfei.zhang@intel.com>
Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
Co-developed-by: Russ Weight <russell.h.weight@intel.com>
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Co-developed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230116100845.6153-11-ilpo.jarvinen@linux.intel.com

2023-01-27 10:47:11 +00:00

Russ Weight

296f5568c6

mfd: intel-m10-bmc: Expose MAC address and count

Create two sysfs entries for exposing the MAC address and count
from the MAX10 BMC register space. The MAC address is the first
in a sequential block of MAC addresses reserved for the FPGA card.
The MAC count is the number of MAC addresses in the reserved block.

Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

2021-02-08 13:54:25 +00:00

Xu Yilun

876611c493

mfd: intel-m10-bmc: Add Intel MAX 10 BMC chip support for Intel FPGA PAC

This patch implements the basic functions of the BMC chip for some Intel
FPGA PCIe Acceleration Cards (PAC). The BMC is implemented using the
Intel MAX 10 CPLD.

This BMC chip is connected to the FPGA by a SPI bus. To provide direct
register access from the FPGA, the "SPI slave to Avalon Master Bridge"
(spi-avmm) IP is integrated in the chip. It converts encoded streams of
bytes from the host to the internal register read/write on the Avalon
bus. So This driver uses the regmap-spi-avmm for register accessing.

Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Reviewed-by: Tom Rix <trix@redhat.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

2020-09-30 17:46:21 +01:00

3 Commits