IF YOU WOULD LIKE TO GET AN ACCOUNT, please write an
email to Administrator. User accounts are meant only to access repo
and report issues and/or generate pull requests.
This is a purpose-specific Git hosting for
BaseALT
projects. Thank you for your understanding!
Только зарегистрированные пользователи имеют доступ к сервису!
Для получения аккаунта, обратитесь к администратору.
There is one more regression introduced by the last build fix:
arch/arm/mach-omap2/timer.c:170:6: error: attribute declaration must precede definition [-Werror,-Wignored-attributes]
void __init omap5_realtime_timer_init(void)
^
arch/arm/mach-omap2/common.h:118:20: note: previous definition is here
static inline void omap5_realtime_timer_init(void)
^
arch/arm/mach-omap2/timer.c:170:13: error: redefinition of 'omap5_realtime_timer_init'
void __init omap5_realtime_timer_init(void)
^
arch/arm/mach-omap2/common.h:118:20: note: previous definition is here
static inline void omap5_realtime_timer_init(void)
Address this by removing the now obsolete #ifdefs in that file and
just building the entire file based on the flag that controls the
omap5_realtime_timer_init function declaration.
Link: https://lore.kernel.org/r/20200529201701.521933-1-arnd@arndb.de
Fixes: d86ad463d6 ("ARM: OMAP2+: Fix regression for using local timer on non-SMP SoCs")
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
On am437x we use also an ARM timer in addition to the dmtimer. As am437x
is not an SMP SoC, we need tick_broadcast() implemented. With the recent
dmtimer changes, Arnd started to see link failures for non-SMP am437x
configuration:
kernel/time/tick-broadcast.o: in function `tick_device_uses_broadcast':
tick-broadcast.c:(.text+0x130): undefined reference to `tick_broadcast'
Let's fix the issue by reverting dmtimer related changes that started
building timer.c only for CONFIG_SOC_HAS_REALTIME_COUNTER. We still
always need timer.c built-in for omap5 and dra7 for timer_probe().
And let's also move am437x tick_broadcast() to board-generic.c as
that's where we now call timer_probe() for am437x. This way we avoid
adding back more ifdefs to timer.c.
Fixes: 2ee04b8854 ("ARM: OMAP2+: Drop old timer code for dmtimer and 32k counter")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
With dmtimer and 32k counter being initialized based on devicetree data,
we can just drop the old timer code.
This still leaves the omap5 and dra7 realtime_counter_init() that
depend on the smc calls and control module platform code for the dra7
quirk init.
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can now init system timers using the dmtimer and 32k counter
based on only devicetree data and drivers/clocksource timers.
Let's configure the clocksource and clockevent, and drop the old
unused platform data.
As we're just dropping platform data, and the early platform data
init is based on the custom ti,hwmods property, we want to drop
both the platform data and ti,hwmods property in a single patch.
Since the dmtimer can use both 32k clock and system clock as the
source, let's also configure the SoC specific default values. The
board specific dts files can reconfigure these with assigned-clocks
and assigned-clock-parents as needed.
Note that similar to omap_init_time_of(), we now need to call
omap_clk_init() also from omap5_realtime_timer_init().
Cc: devicetree@vger.kernel.org
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
request_irq() is preferred over setup_irq(). Invocations of setup_irq()
occur after memory allocators are ready.
Per tglx[1], setup_irq() existed in olden days when allocators were not
ready by the time early interrupts were initialized.
Hence replace setup_irq() by request_irq().
[1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanos
Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We have local timers on Cortex-A9, so using the gptimer option makes no
sense. Let's just drop it for omap4 to simplify the timer options a bit.
If this is really needed, it can be still done by specifying dts properties
in the board specific file for assigned-clocks and assigned-clock-parents.
This gets us a bit closer to start dropping legacy platform data for
gptimers except for timer1 that is used for system clockevent.
Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As of commit d1dabab284 ("ARM: OMAP2+: Clean up
omap4_local_timer_init"), this header file is no longer used.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Late omap soc changes for v4.18 merge window
This series contains two omap1 ams-delta GPIO clean-up patches to get
started with removal of hard-coded GPIO numbers from drivers. And then
the removal of board mach includes from drivers. The second patch mostly
touches the ams-delta audio driver but is included here because of the
removal of the latch gpios and is acked by Mark Brown.
And there are two more am437x related PM patches to save and restore
control module and timer registers for RTC only suspend mode. Looks like
the patch title for the timer changes is a bit misleading, not all the
timer code is yet living under drivers/clocksource. But I had already
pushed out the branch before I noticed this.
* tag 'omap-for-v4.18/soc-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
OMAP: CLK: CLKSRC: Add suspend resume hooks
ARM: AM43XX: Add functions to save/restore am43xx control registers
ASoC: ams_delta: use GPIO lookup table
ARM: OMAP1: ams-delta: add GPIO lookup tables
Signed-off-by: Olof Johansson <olof@lixom.net>
Add the save and restore for clksrc as part of suspend and resume
so that it saves the counter value and restores. This is needed in
modes like rtc+ddr in self-refresh not doing this stalls the time.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
If a system timer is configured with an interrconnect target module in
the dts, the ti,hwmods and module fck are at the interconnect target
level. Then there's a separate fck for the timer child device.
If the child device has a separate functional clock, we need to configure
it directly. For example, timer clk clkctrl clock bit 0 is the module
clock for the interconnect target, and bit 24 being the functional clock
for the timer IP.
For system timers, we already mark them as disabled. Now must also mark
the interconnect target module as disabled to prevent ti-sysc to manage
it instead of the system timer.
Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Looks like these functions don't do anything in the mainline kernel so
we can just drop it.
Note that we must now also remove ir-rx51 pdata as it relies on the dummy
platform data that does not do anything. And ir-rx51 is calling a pdata
callback that doesn't do anything without checking if it exists first.
For configuring device specific minimal latencies, the interface to use
is pm_qos_add_request(). For an example, see what was done in commit
9834ffd1ec ("ASoC: omap-mcbsp: Add PM QoS support for McBSP to prevent
glitches"). I've added some comments to ir-rx51 so people using it can
add pm_qos support and test it.
Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Cc: Kevin Hilman <khilman@kernel.org>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The header file is currently under plat-omap directory
under arch/omap. Move this out to an accessible place.
No Code changes done to the header file and renamed to timer-ti-dm.h.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
When more than one GP timers are used as kernel system timers and the
corresponding nodes in device-tree are marked with the same "disabled"
property, then the "attr" field of the property will be initialized
more than once as the property being added to sys file system via
__of_add_property_sysfs().
In __of_add_property_sysfs(), the "name" field of pp->attr.attr is set
directly to the return value of safe_name(), without taking care of
whether it's already a valid pointer to a memory block. If it is, its
old value will always be overwritten by the new one and the memory block
allocated before will a "ghost", then a kmemleak happened.
That the same "disabled" property being added to different nodes of device
tree would cause that kind of kmemleak overhead, at least once.
To fix it, allocate the property dynamically, and delete static one.
Signed-off-by: Qi Hou <qi.hou@windriver.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Pull ARM SoC platform updates from Arnd Bergmann:
"SoC platform changes (arch/arm/mach-*). This merge window, the bulk is
for a few platforms:
- Andres Färber adds initial support for the Actions Semi S500 (aka
'owl') platform, a close relative of the S900 platform he adds for
arm64.
- in mach-omap2, we remove more legacy code
- Rockchips gains support for the RV1108 SoC designed for camera
applications.
- For Atmel, we gain support for MMU-less SoCs (SAME70/V71/S70/V70)
- Minor updates for other platforms, including davinci, s3c64xx,
prima2, stm32, broadcom nsp, amlogic, pxa, imx and renesas"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (74 commits)
ARM: owl: smp: Drop bogus holding pen
ARM: owl: Drop custom machine
ARM: owl: smp: Implement SPS power-gating for CPU2 and CPU3
soc: actions: owl-sps: Factor out owl_sps_set_pg() for power-gating
soc: actions: Add Owl SPS
dt-bindings: power: Add Owl SPS power domains
MAINTAINERS: Update Actions Semi section with SPS
ARM: owl: Implement CPU enable-method for S500
MAINTAINERS: Add Actions Semi Owl section
ARM: Prepare Actions Semi S500
ARM: socfpga: Increase max number of GPIOs
ARM: stm32: Introduce MACH_STM32F469 flag
ARM: prima2: remove redundant select CPU_V7
ARM: davinci: fix const warnings
ARM: shmobile: pm-rmobile: Use GENPD_FLAG_ALWAYS_ON
ARM: OMAP4: hwmod_data: add SHAM crypto accelerator
ARM: OMAP4: hwmod data: add des
ARM: OMAP4: hwmod data: add aes2
ARM: OMAP4: hwmod data: add aes1
ARM: pxa: Delete an error message for a failed memory allocation in pxa3xx_u2d_probe()
...
The mux clock handle shall be provided via "fck" DT handle. This avoids
the need to lookup the main clock via hwmod core, which will not work
with the clkctrl clock support anymore; the main clock is not going to
be a mux.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We are now booting all mach-omap2 in device tree only mode.
Any code that is only called in legacy boot mode where
of_have_populated_dt() is not set is safe to remove now.
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OMAP timer code registers two timers - one as clocksource
and one as clockevent. Since AM33XX has only one usable timer
in the WKUP domain one of the timers needs suspend-resume
support to restore the configuration to pre-suspend state.
commit adc78e6b99 ("timekeeping: Add suspend and resume
of clock event devices") introduced .suspend and .resume
callbacks for clock event devices. Leverage these
callbacks to have AM33XX clockevent timer behave properly
across system suspend. Extend the use of the .suspend and
.resume callbacks used by am335x clockevent to am437x as well.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The commit 55ee7017ee ("arm: omap2: board-generic: use
omap4_local_timer_init for AM437x") unintentionally changes the
clocksource devices for AM437x from OMAP GP Timer to SyncTimer32K.
Unfortunately, the SyncTimer32K is starving from frequency deviation
as mentioned in commit 5b5c013591 ("ARM: OMAP2+: AM43x: Use gptimer
as clocksource") and, as reported by Franklin [1], even its monotonic
nature is under question (most probably there is a HW issue, but it's
still under investigation).
Taking into account above facts It's reasonable to rollback to the use
of omap3_gptimer_timer_init().
[1] http://www.spinics.net/lists/linux-omap/msg127425.html
Fixes: 55ee7017ee ("arm: omap2: board-generic: use
omap4_local_timer_init for AM437x")
Reported-by: Cooper Jr., Franklin <fcooper@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
There is no point in having an extra type for extra confusion. u64 is
unambiguous.
Conversion was done with the following coccinelle script:
@rem@
@@
-typedef u64 cycle_t;
@fix@
typedef cycle_t;
@@
-cycle_t
+u64
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: John Stultz <john.stultz@linaro.org>
With the introduction of hwmod module clocks, the name of the hwmod
main clk may not be available before hwmod setup, as hwmod setup
may lookup the main clock dynamically based on the hwmod name.
Thus, change the order of hwmod setup and main clock handling for
the timer code, to make sure the main clock is going to be
available.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
A few platforms are currently missing clocksource_probe() completely
in their time_init functionality. On OMAP3430 for example, this is
causing cpuidle to be pretty much dead, as the counter32k is not
going to be registered and instead a gptimer is used as a clocksource.
This will tick in periodic mode, preventing any deeper idle states.
While here, also drop one unnecessary check for populated DT before
existing clocksource_probe() call.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Pull ARM SoC platform updates from Olof Johansson:
"Updates for new platform support:
- New platform: Tango4 from Sigma Designs.
- Broadcom BCM2836 (Raspberry Pi 2 SoC)
- Enable cpufreq on Freescale i.MX7D
- Rockchip: SMP support for rk3036, general support for rk3228
- SMP support on Broadcom Kona and NSP
- Cleanups for OMAP removing legacy IOMMU data
+ a bunch of misc fixes and tweaks for various platforms"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (46 commits)
ARM: tango: Fix UP build issues
ARM: tango: pass ARM arch level for smc.S
ARM: bcm2835: Add Kconfig support for bcm2836
ARM: OMAP2+: Add support for dm814x and dra62x usb
ARM: OMAP2+: Add mmc hwmod entries for dm814x
ARM: OMAP2+: Update 81xx clock and power domains for default, active and sgx
ARM: OMAP2+: Fix SoC detection for dra62x j5-eco
ARM: tango4: Initial platform support
ARM: bcm2835: Add a compat string for bcm2836 machine probe
dt-bindings: Add root properties for Raspberry Pi 2
ARM: imx: select SRC for i.MX7
ARM: uniphier: select PINCTRL
ARM: OMAP2+: Remove device creation for omap-pcm-audio
ARM: OMAP1: Remove device creation for omap-pcm-audio
ARM: rockchip: enable support for RK3228 SoCs
ARM: rockchip: use const and __initconst for rk3036 smp_operations
ARM: zynq: Select ARCH_HAS_RESET_CONTROLLER
ARM: BCM: Add SMP support for Broadcom 4708
ARM: BCM: Add SMP support for Broadcom NSP
ARM: BCM: Clean up SMP support for Broadcom Kona
...
System will misbehave in the following case:
- AM43XX only build (UP);
- CONFIG_CPU_IDLE=y
- ARM TWD timer enabled and selected as clockevent device.
In the above case, It's expected that broadcast timer will be used as
backup timer when CPUIdle will put MPU in low power states where ARM
TWD will stop and lose its context. But, the CONFIG_SMP might not be
selected when kernel is built for AM43XX SoC only and, as result,
GENERIC_CLOCKEVENTS_BROADCAST option will not be selected also. This
will break CPUIdle and System will stuck in low power states.
Hence, fix it by selecting GENERIC_CLOCKEVENTS_BROADCAST option for
AM43XX SoCs always and add empty tick_broadcast() function
implementation - no need to send any IPI on UP. After this change
timer1 will be selected as broadcast timer the same way as for SMP,
and CPUIdle will work properly.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Timer 12 on DRA7 SoCs is reserved for secure usage on high-secure (HS)
devices. The timer cannot be used by the kernel on HS devices, but is
available on regular general purpose (GP) devices. This is similar to the
behavior on OMAP3 devices, so extend the logic used in commit ad24bde8f1
("ARM: OMAP3: Dynamically disable secure timer nodes for secure devices")
to remove the secure timer on DRA7xx SoCs at run-time based on the SoC
device type.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Pull ARM SoC cleanups from Olof Johansson:
"Again we have a sizable (but not huge) cleanup branch with a net delta
of about -3k lines.
Main contents here is:
- A bunch of development/cleanup of a few PXA boards
- Removal of bockw platforms on shmobile, since the platform has now
gone completely multiplatform. Whee!
- move of the 32kHz timer on OMAP to a proper timesource
- Misc cleanup of older OMAP material (incl removal of one board
file)
- Switch over to new common PWM lookup support for several platforms
There's also a handful of other cleanups across the tree, but the
above are the major pieces"
* tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (103 commits)
ARM: OMAP3: hwmod data: Remove legacy mailbox data and addrs
ARM: DRA7: hwmod data: Remove spinlock hwmod addrs
ARM: OMAP4: hwmod data: Remove spinlock hwmod addrs
ARM: DRA7/AM335x/AM437x: hwmod: Remove gpmc address space from hwmod data
ARM: Remove __ref on hotplug cpu die path
ARM: Remove open-coded version of IRQCHIP_DECLARE
arm: omap2: board-generic: use omap4_local_timer_init for AM437x
ARM: DRA7/AM335x/AM437x: hwmod: Remove elm address space from hwmod data
ARM: OMAP: Remove duplicated operand in OR operation
clocksource: ti-32k: make it depend on GENERIC_CLOCKSOURCE
ARM: pxa: remove incorrect __init annotation on pxa27x_set_pwrmode
ARM: pxa: raumfeld: make some variables static
ARM: OMAP: Change all cpu_is_* occurences to soc_is_* for id.c
ARM: OMAP2+: Rename cpu_is macros to soc_is
arm: omap2: timer: limit hwmod usage to non-DT boots
arm: omap2+: select 32k clocksource driver
clocksource: add TI 32.768 Hz counter driver
arm: omap2: timer: rename omap_sync32k_timer_init()
arm: omap2: timer: always call clocksource_of_init() when DT
arm: omap2: timer: move realtime_counter_init() around
...
now that we have a working 32k clocksource driver,
we can limit HWMOD usage to non-DT boots and rely
on clocksource_of_init() every time we boot
with DT.
While at that, also make sure that we don't disable
the 32-counter device so it gets probed by its driver.
Signed-off-by: Felipe Balbi <balbi@ti.com>
this function is not only about the 32k sync
timer, it's OMAP's generic init_time implementation.
Let's rename it to make that detail easier to
notice.
Signed-off-by: Felipe Balbi <balbi@ti.com>
If booting with DT, let's make sure to always
call clocksource_of_init() as this will make
it easier to move timer code to drivers/clocksource
in the future.
Signed-off-by: Felipe Balbi <balbi@ti.com>
instead of constantly defining a small wrapper
around __omap_sync32k_timer_init(), let's define
a generic one which can be used by all OMAPs.
Signed-off-by: Felipe Balbi <balbi@ti.com>
__omap_sync32k_timer_init(), now takes the clock
source as a parameter. This means we no longer need
__omap_gptimer_init().
Note that __omap_sync32k_timer_init() will be
renamed in a follow-up patch as it's not longer 32k
source specific.
Signed-off-by: Felipe Balbi <balbi@ti.com>
as it turns out, __omap_gptimer_init() and
__omap_sync32k_timer_init() are essentially
the same thing, but __omap_gptimer_init() wants
to always use gptimer.
Instead of forcing all those devices to pass
a use_gptimer cmdline argument, we add a new
function argument to __omap_sync32k_timer_init()
in preparation to deleting __omap_gptimer_init().
On a follow-up patch, we will remove uses of
__omap_gptimer_init() and replace them with
__omap_sync32k_timer_init() and pass the last
argument as true.
Signed-off-by: Felipe Balbi <balbi@ti.com>
those macros just make it a lot more difficult
to grep around and actually find similarities.
In this patch, we will simply remove them and
replace with actual functions and later commits
will come to further clean this up.
Signed-off-by: Felipe Balbi <balbi@ti.com>
omap4_local_timer_init() can be used by other
platforms as is. At least AM437x wants to use
it. Instead of making omap4-only and providing
a stub for builds without OMAP4, we can just
make sure that function is always available
for all SoCs that need it.
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
When bringing up a new SoC we needlessly prevent booting at timer
init if timer clock_set_parent fails. This can fail if the system
is booting on bootloader configured PLL values until the clock
framework driver for the PLL is implemented.
Let's just WARN instead, this will provide helpful information
for anybody bringing up a new SoC what needs to be fixed.
This allows to boot dm814x that's still missing the PLL driver.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Pull ARM SoC platform updates from Olof Johansson:
"New or improved SoC support:
- add support for Atmel's SAMA5D2 SoC
- add support for Freescale i.MX6UL
- improved support for TI's DM814x platform
- misc fixes and improvements for RockChip platforms
- Marvell MVEBU suspend/resume support
A few driver changes that ideally would belong in the drivers branch
are also here (acked by appropriate maintainers):
- power key input driver for Freescale platforms (svns)
- RTC driver updates for Freescale platforms (svns/mxc)
- clk fixes for TI DM814/816X
+ a bunch of other changes for various platforms"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits)
ARM: rockchip: pm: Fix PTR_ERR() argument
ARM: imx: mach-imx6ul: Fix allmodconfig build
clk: ti: fix for definition movement
ARM: uniphier: drop v7_invalidate_l1 call at secondary entry
memory: kill off set_irq_flags usage
rtc: snvs: select option REGMAP_MMIO
ARM: brcmstb: select ARCH_DMA_ADDR_T_64BIT for LPAE
ARM: BCM: Enable ARM erratum 798181 for BRCMSTB
ARM: OMAP2+: Fix power domain operations regression caused by 81xx
ARM: rockchip: enable PMU_GPIOINT_WAKEUP_EN when entering shallow suspend
ARM: rockchip: set correct stabilization thresholds in suspend
ARM: rockchip: rename osc_switch_to_32k variable
ARM: imx6ul: add fec MAC refrence clock and phy fixup init
ARM: imx6ul: add fec bits to GPR syscon definition
rtc: mxc: add support of device tree
dt-binding: document the binding for mxc rtc
rtc: mxc: use a second rtc clock
ARM: davinci: cp_intc: use IRQCHIP_SKIP_SET_WAKE instead of irq_set_wake callback
soc: mediatek: Fix SCPSYS compilation
ARM: at91/soc: add basic support for new sama5d2 SoC
...
ARM: OMAP2+: PRCM and hwmod changes for v4.3
This series adds:
- I/O wakeup support for AM43xx
- register lock and unlock support to the hwmod code (needed for the RTC
IP blocks on some chips)
- several fixes for sparse warnings and an unnecessary null pointer test
- a DRA7xx clockdomain configuration workaround, to deal with some hardware
bugs
Basic build, boot, and PM tests are here:
http://www.pwsan.com/omap/testlogs/hwmod-prcm-for-v4.3/20150723080012/
Since I do not have an AM43xx or DRA7xx device, I can't test on those
platforms.
Migrate omap2 driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.
This also enables us to implement callbacks for new states of clockevent
devices, for example: ONESHOT_STOPPED.
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Inspired by a patch from Felipe Balbi <balbi@ti.com>, we can
now get rid of most the code in omap4_local_timer_init.
Omap4 is now device tree only.. And we have not properly supported
omap4 ES1.0 revision for a really long time AFAIK.
Let's just remove all that code to simplify things. This assumes
we have arm,cortex-a9-twd-timer entry in the omap4.dtsi file, which
we do.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The of_node_put() function tests whether its argument is NULL and then
returns immediately if so. Furthermore, the kerneldoc for
of_node_put() explicitly supports passing in a NULL pointer as its
argument. Thus the test around the call is not needed.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
[paul@pwsan.com: dropped the omap_device.c and omap_hwmod.c changes for
now, edited the commit message accordingly and to note the documented
"contract"]
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
With recent changes to use determine_rate, the comparison of two
clocks won't work without clk_is_match that does __clk_get_hw
on the clocks first.
As we've been unconditionally already calling clk_set_parent
already because of the bogus comparison, let's just remove the
check as suggested by Stephen Boyd <sboyd@codeaurora.org>.
Cc: Michael Turquette <mturquette@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Pull ARM SoC non-critical fixes from Olof Johansson:
"Here's a small collection of fixes accrued during the last release
that weren't considered severe enough to merge during the -rc series.
A few of these are around resurrecting TI81xx support that's been
broken for quite a while, the rest are smaller fixes -- most for PXA
but a few across the board.
There are also some updates to MAINTAINERS here, in particular for
Broadcom platforms"
* tag 'fixes-non-critical-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
MAINTAINERS: fix git repositories for Broadcom SoCs
ARM: pxa: fix broken isa interrupts for zeus and viper
ARM: DRA7: hwmod: Fix boot crash with DEBUG_LL enabled on UART3
ARM: OMAP: DRA7: hwmod: Make gpmc software supervised as the smart idle is broken
ARM: AM43xx: hwmod: set DSS submodule parent hwmods
ARM: OMAP2+: hwmod: print error if wait_target_ready() failed
MAINTAINERS: add maintainer for OMAP hwmod data
ARM: OMAP2+: Disable omap3 PM init for ti81xx
ARM: OMAP2+: Fix reboot for 81xx
ARM: OMAP2+: Fix dm814 and dm816 for clocks and timer init
ARM: OMAP2+: Fix ti81xx class type
ARM: OMAP2+: Fix ti81xx devtype
ARM: OMAP2+: Fix error handling for omap2_clk_enable_init_clocks
MAINTAINERS: add a git entry for BMIPS-based BCM7xxx SoCs
MAINTAINERS: add a git entry for BCM7xxx ARM-based SoCs
MAINTAINERS: update Broadcom Cygnus SoC git tree
MAINTAINERS: move BCM63xx ARM-based SoCs git tree
hx4700: regulator: declare full constraints
ARM: pxa: add regulator_has_full_constraints to spitz board file
ARM: pxa: add regulator_has_full_constraints to poodle board file
...
Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
crystal is not enabled at power up. Instead the CPU falls back to using
an emulation for the 32KHz clock which is SYSCLK1/610. SYSCLK1 is usually
20MHz on boards so far (which gives an emulated frequency of 32.786KHz),
but can also be 19.2 or 27MHz which result in much larger drift.
Since this is used to drive the master counter at 32.768KHz * 375 /
2 = 6.144MHz, the emulated speed for 20MHz is of by 570ppm, or about 43
seconds per day, and more than the 500ppm NTP is able to tolerate.
Checking the CTRL_CORE_BOOTSTRAP register can determine if the CPU
is using the real 32.768KHz crystal or the emulated SYSCLK1/610, and
by known that the real counter frequency can be determined and used.
The real speed is then SYSCLK1 / 610 * 375 / 2 or SYSCLK1 * 75 / 244.
Signed-off-by: Len Sorensen <lsorense@csclub.uwaterloo.ca>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The switch statement of the possible list of SYSCLK1 frequencies is
missing a 0 in 4 out of the 7 frequencies.
Fixes: fa6d79d276 ("ARM: OMAP: Add initialisation for the real-time counter")
Cc: stable@vger.kernel.org # v3.7+
Signed-off-by: Len Sorensen <lsorense@csclub.uwaterloo.ca>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
