11c7faa61d
drm/i915/dg2: Add additional HDMI pixel clock frequencies
...
Using the BSPEC algorithm add addition HDMI pixel clocks to the existing
table.
v2: remove 297000 unused entry
Cc: Matt Roper <matthew.d.roper@intel.com >
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com >
Signed-off-by: Taylor, Clinton A <clinton.a.taylor@intel.com >
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com >
[mattrope: Fixed minor whitepsace issue flagged by checkpatch]
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220801234856.2832317-1-clinton.a.taylor@intel.com
2022-08-24 12:34:07 -07:00
781c336a6c
drm/i915/mpllb: move mpllb state check to intel_snps_phy.c
...
Keep the mpllb implementation details together in intel_snps_phy.c. Also
declutter intel_display.c.
v2: intel_mpllb_verify_state -> void intel_mpllb_state_verify (Ville)
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/e7340bb0e399aeb2676c4820461187eeb1d4db15.1655372759.git.jani.nikula@intel.com
2022-06-17 11:54:54 +03:00
4f543d664c
drm/i915: Require an exact DP link freq match for the DG2 PLL
...
No idea why the DG2 PLL DP link frequency calculation is allowing
a non-exact match. That makes no sense so get rid of it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-24-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
Acked-by: Matt Roper <matthew.d.roper@intel.com >
2022-05-31 21:04:46 +03:00
edd34368c4
drm/i915/dg2: Support 4k@30 on HDMI
...
This patch adds a fix to support 297MHz of dot clock by calculating
the pll values using synopsis algorithm.
This will help to support 4k@30 mode for HDMI monitors on DG2.
v2: As per the algorithm, set MPLLB VCO range control bits to 3,
in register SNPS_PHY_MPLLB_DIV for 297Mhz. (Matt)
v3: Fix typo. (Ankit)
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com >
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com >
Reviewed-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220525080401.1253511-1-ankit.k.nautiyal@intel.com
2022-05-25 07:46:12 -07:00
b4eb76d82a
drm/i915/dg2: Skip output init on PHY calibration failure
...
If one of our PHYs fails to complete calibration, we should skip the
general initialization of the corresponding output. Most likely this is
going to happen on outputs that don't actually exist on the board; in
theory we should have already decided to skip this output based on the
VBT, but we can't always rely on the VBT being accurate.
Cc: Lucas De Marchi <lucas.demarchi@intel.com >
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220223165421.3949883-1-matthew.d.roper@intel.com
2022-02-24 17:16:51 -08:00
9b693453a4
drm/i915/dg2: Drop 38.4 MHz MPLLB tables
...
Our early understanding of DG2 was incorrect; since the 5th display
isn't actually a Type-C output, 38.4 MHz input clocks are never used on
this platform and we can drop the corresponding MPLLB tables.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com >
Cc: José Roberto de Souza <jose.souza@intel.com >
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Ramalingam C <ramalingam.c@intel.com >
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com >
Reviewed-by: Uma Shankar <uma.shankar@intel.com >
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220218010328.183423-2-lucas.demarchi@intel.com
2022-02-18 16:03:31 -08:00
d1af7b6f91
drm/i915: Fix for PHY_MISC_TC1 offset
...
Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E.
The PORT_TC1 port is not yet enabled properly in the driver, but
intel_phy_snps.c is relying on intel_phy_is_snps() to filter out
unavailable phys. That function was already considering the last phy as
available. Just correct the offset of the last phy to 0x64C14 as the
rest of the support for it is coming on next commits.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Jouni Högander <jouni.hogander@intel.com >
Signed-off-by: Ramalingam C <ramalingam.c@intel.com >
Reviewed-by: Uma Shankar <uma.shankar@intel.com >
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com >
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220218010328.183423-1-lucas.demarchi@intel.com
2022-02-18 16:03:30 -08:00
84073e568e
drm/i915/dg2: Print PHY name properly on calibration error
...
We need to use phy_name() to convert the PHY value into a human-readable
character in the error message.
Fixes: a6a128116ematthew.d.roper@intel.com >
Reviewed-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220215163545.2175730-1-matthew.d.roper@intel.com
2022-02-17 16:10:25 -08:00
c5274e86da
drm/i915/snps: convert to drm device based logging
...
Prefer drm device based logging. Do some dev_priv->i915 conversions
while at it.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com >
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/ca6908452a63bd74a9c9d75ecd295182c80c7205.1642769982.git.jani.nikula@intel.com
2022-01-24 15:19:51 +02:00
aa1d6068a4
drm/i915: Move SNPS PHY registers to their own header
...
These registers are only needed in a couple files and on specific
platforms; let's keep them separate from the general register pool.
v2:
- Don't forget to include i915_reg_defs.h (Jani)
- Ensure include guard matches header name (Jani)
Cc: Jani Nikula <jani.nikula@linux.intel.com >
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220111051600.3429104-9-matthew.d.roper@intel.com
2022-01-11 14:03:25 -08:00
61b98486e4
drm/i915/snps: use div32 version of MPLLB word clock for UHBR
...
The mode set sequence for 128b/132b requires setting the div32 version
of MPLLB clock.
Bspec: 53880, 54128
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20211202144456.2541305-1-jani.nikula@intel.com
2021-12-07 10:41:07 +02:00
3e9cf8f055
drm/i915: Query the vswing levels per-lane for snps phy
...
Prepare for per-lane drive settings by querying the desired vswing
level per-lane.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-12-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
2021-11-03 19:45:46 +02:00
247c8a7379
drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs
...
The struct itself already has sufficient namespace. No need to
duplicate it in the members.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
2021-10-14 18:45:35 +03:00
d0920a4557
drm/i915: Pass the lane to intel_ddi_level()
...
In order to have per-lane drive settings we need intel_ddi_level()
to accept the lane as a parameter. That is, the eventual goal is to
call intel_ddi_level() once for each lane. For now we just pass in
a hardcoded 0 and use the same settings for every lane. Ie. no
change in behaviour yet.
Reviewed-by: Imre Deak <imre.deak@intel.com >
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20211001130107.1746-9-ville.syrjala@linux.intel.com
2021-10-04 13:04:36 +03:00
2c63e0f92e
drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level()
...
All callers of intel_ddi_level() duplicate the check+WARN
to make sure the returned level is actually present in the
appropriate buf_trans table. Let's push that stuff into
intel_ddi_level() so the callers don't have to worry about it.
Reviewed-by: Imre Deak <imre.deak@intel.com >
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20211001130107.1746-7-ville.syrjala@linux.intel.com
2021-10-04 13:01:28 +03:00
193299ad9d
drm/i915: Nuke useless .set_signal_levels() wrappers
...
Now that .set_signal_levels() is used for HDMI as well, we can
remove the extra level of indirection and just plug the correct
stuff straight into .set_signal_levels().
Reviewed-by: Imre Deak <imre.deak@intel.com >
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20211001130107.1746-5-ville.syrjala@linux.intel.com
2021-10-04 12:42:55 +03:00
e505d76404
drm/i915: s/ddi_translations/trans/
...
"ddi_translations" is a bit too long, let's shorten it to just "trans".
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20210927182455.27119-2-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com >
2021-09-30 23:48:37 +03:00
45cbbe50cc
drm/i915/dg2: UHBR tables added for pll programming
...
UHBR modes has higher link rate and added new values for programming
mpll of SNPS phy. No change in sequence, only the pll parameters
are different for UHBR modes.
Reviewed-by: Jani Nikula <jani.nikula@intel.com >
Signed-off-by: Animesh Manna <animesh.manna@intel.com >
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20210827103843.527-1-jani.nikula@intel.com
2021-08-30 13:24:44 +03:00
3a8e7fd66e
drm/i915/snps: constify struct intel_mpllb_state arrays harder
...
The tables should be const arrays of const pointers, not just arrays of
const pointers.
Cc: Matt Roper <matthew.d.roper@intel.com >
Reviewed-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20210825145811.4227-1-jani.nikula@intel.com
2021-08-26 12:06:34 +03:00
3b4da8315a
drm/i915/dg2: use existing mechanisms for SNPS PHY translations
...
We use encoder->get_buf_trans() in many places, for example
intel_ddi_dp_voltage_max(), and the hook was set to some old platform's
function for DG2 SNPS PHY. Convert SNPS PHY to use the same translation
mechanisms as everything else.
Cc: Manasi Navare <manasi.d.navare@intel.com >
Cc: Matt Roper <matthew.d.roper@intel.com >
Reviewed-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20210813115151.19290-2-jani.nikula@intel.com
2021-08-13 22:32:16 +03:00
7711749a60
drm/i915/dg2: Update lane disable power state during PSR
...
The PSR enable/disable sequences now require that we program an extra
register in the PHY to adjust the lane disable power setting.
Bspec: 49274
Bspec: 53885
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com >
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com >
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-29-matthew.d.roper@intel.com
2021-07-29 09:32:54 -07:00
a6a128116e
drm/i915/dg2: Wait for SNPS PHY calibration during display init
...
Initialization of the PHY is handled by the hardware/firmware, but the
driver should wait up to 25ms for the PHY to report that its calibration
has completed.
Bspec: 49189
Bspec: 50107
Cc: Matt Atwood <matthew.s.atwood@intel.com >
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-28-matthew.d.roper@intel.com
2021-07-29 09:32:48 -07:00
a046a0daa3
drm/i915/dg2: Add vswing programming for SNPS phys
...
Vswing programming for SNPS PHYs is just a single step -- look up the
value that corresponds to the voltage level from a table and program it
into the SNPS_PHY_TX_EQ register.
Bspec: 53920
Cc: Matt Atwood <matthew.s.atwood@intel.com >
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-26-matthew.d.roper@intel.com
2021-07-29 09:07:05 -07:00
865b73ea18
drm/i915/dg2: Add MPLLB programming for HDMI
...
At the moment we don't have a proper algorithm that can be used to
calculate PHY settings for arbitrary HDMI link rates. The PHY tables
here should support the regular modes of real-world HDMI monitors.
Bspec: 54032
Cc: Matt Atwood <matthew.s.atwood@intel.com >
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com >
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-25-matthew.d.roper@intel.com
2021-07-29 09:06:01 -07:00
2908100804
drm/i915/dg2: Add MPLLB programming for SNPS PHY
...
DG2's SNPS PHYs incorporate a dedicated port PLL called MPLLB which
takes the place of the shared DPLLs we've used on past platforms. Let's
add the MPLLB programming sequences; they'll be plugged into the rest of
the code in future patches.
Bspec: 54032
Bspec: 53881
Cc: Lucas De Marchi <lucas.demarchi@intel.com >
Signed-off-by: Matt Roper <matthew.d.roper@intel.com >
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com >
Signed-off-by: Jani Nikula <jani.nikula@intel.com >
Signed-off-by: Nidhi Gupta <nidhi1.gupta@intel.com >
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-24-matthew.d.roper@intel.com
2021-07-29 09:05:25 -07:00
