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60 Commits

Author SHA1 Message Date
Alex Deucher
f8a69a8022 drm/amdgpu/nv: add asic func for fetching vbios from rom directly 
Needed as a fallback if the vbios can't be fetched by other means.

Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-11-22 14:35:10 -05:00
Kevin Wang
2af8153126 drm/amdgpu: fix sysfs interface pcie_replay_count error on navi asic 
the asic callback function of get_pcie_replay_count is not implement on navi asic,
it will cause null pinter error when read this interface.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-11-07 18:08:07 -05:00
Jiange Zhao
b4def3744b drm/amdgpu/SRIOV: SRIOV VF doesn't support BACO 
SRIOV VF doesn't support BACO.

Only PF with BACO capability can do it.

Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-10-30 11:06:51 -04:00
Marek Olšák
664fe85a2d drm/amdgpu: Allow reading more status registers on si/cik 
Allow userspace to read the same status registers for every family.
Based on commit c7890fea, added any of these registers if defined in
the include files of each architecture.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-10-25 16:50:10 -04:00
Alex Deucher
2c9a0c66d5 drm/amdgpu: don't increment vram lost if we are in hibernation 
We reset the GPU as part of our hibernation sequence so we need
to make sure we don't mark vram as lost in that case.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111879
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-10-03 09:11:05 -05:00
Yong Zhao
923c087a1f drm/amdgpu: Add the HDP flush support for Navi 
The HDP flush support code was missing in the nbio and nv files.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-10-03 09:11:05 -05:00
Jiange Zhao
a4ac7693f8 drm/amdgpu/SRIOV: Navi10/12 VF doesn't support SMU 
In SRIOV case, SMU and powerplay are handled in HV.

VF shouldn't have control over SMU and powerplay.

Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-09-16 10:16:14 -05:00
Jiange Zhao
b05b69036f drm/amdgpu: For Navi12 SRIOV VF, register mailbox functions 
Mailbox functions and interrupts are only for Navi12 VF.

Register functions and irqs during initialization.

Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-09-16 10:15:20 -05:00
Hawking Zhang
bebc076285 drm/amdgpu: switch to new amdgpu_nbio structure 
no functional change, just switch to new structures

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-09-13 17:11:03 -05:00
Petr Cvek
20c14ee135 drm/amdgpu: Fix undefined dm_ip_block for navi12 
There is missing "if defined" CONFIG_DRM_AMD_DC block for non DC
configurations. This will cause link error. The patch is fixing that.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=110979
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-30 15:37:17 -05:00
Monk Liu
e352625796 drm/amdgpu: introduce vram lost for reset (v2) 
for SOC15/vega10 the BACO reset & mode1 would introduce vram lost
in high end address range, current kmd's vram lost checking cannot
catch it since it only check very ahead visible frame buffer

v2:
cover NV as well

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-29 15:52:32 -05:00
Xiaojie Yuan
5ef3b8acdc drm/amdgpu: enable athub powergating for navi12 
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-29 15:52:32 -05:00
Xiaojie Yuan
c1653ea05b drm/amdgpu: enable vcn powergating for navi12 
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-29 15:52:31 -05:00
YueHaibing
6892c1f866 drm/amdgpu: remove set but not used variable 'psp_enabled' 
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/amdgpu/nv.c: In function 'nv_common_early_init':
drivers/gpu/drm/amd/amdgpu/nv.c:471:7: warning:
 variable 'psp_enabled' set but not used [-Wunused-but-set-variable]

It's not used since inroduction in
commit c6b6a42175 ("drm/amdgpu: add navi10 common ip block (v3)")

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-21 22:18:51 -05:00
Kenneth Feng
6da6c27928 drm/amd/amdgpu: disable MMHUB PG for navi10 
Disable MMHUB PG for navi10 according to the production requirement.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-21 22:18:05 -05:00
Xiaojie Yuan
65872e59d6 drm/amdgpu: enable vcn clock gating for navi12 
enables vcn medium grained clock gating

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
ca51678db4 drm/amdgpu: enable athub clock gating for navi12 
enables athub medium grained clock gating and memory light sleep

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
fbe0bc5794 drm/amdgpu: enable ih clock gating for navi12 
enables ih clock gating

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
8b797b3d30 drm/amdgpu: enable mmhub clock gating for navi12 
enables mmhub medium grained clock gating and memory light sleep

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
358ab97f53 drm/amdgpu: enable sdma clock gating for navi12 
enables sdma medium grained clock gating and memory light sleep

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
5211c37a34 drm/amdgpu: enable hdp clock gating for navi12 
enables hdp medium grained clock gating and memory light sleep

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
dca009e71c drm/amdgpu: enable gfx clock gatings for navi12 
enables following gfx clock gating features:

- medium grained clock gating
- medium grained light sleep
- coarse grained clock gating
- cp memory light sleep
- rlc memory light sleep

CGLS (Coarse Grained Light Sleep) will break s3, so don't enable it.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-12 12:47:47 -05:00
Xiaojie Yuan
b5c7385640 drm/amdgpu/discovery: move common discovery code out of navi1*_reg_base_init() 
move amdgpu_discovery_reg_base_init() from navi1*_reg_base_init() to a
common function nv_reg_base_init().

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-06 13:53:05 -05:00
tiancyin
35ef88fa11 drm/amdgpu/soc15: fix external_rev_id for navi14 
fix the hard code external_rev_id.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-06 13:52:58 -05:00
Leo Li
078655d982 drm/amdgpu: Add nv12 DC ip block 
Load DC and amdgpu display manager

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Boyuan Zhang
400e9c5ea6 drm/amdgpu: enable DPG mode for Navi12 
Enable Dynamic Power Gating VCN for Navi12.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Boyuan Zhang
1fbed280a2 drm/amdgpu: add VCN ip block for Navi12 
Add VCN2 ip block for Navi12

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Xiaojie Yuan
6b66ae2e55 drm/amdgpu: add psp ip block for navi12 
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Xiaojie Yuan
7f47efeb9e drm/amdgpu: add smu ip block for navi12 
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:41 -05:00
Xiaojie Yuan
7990202903 drm/amdgpu: enable virtual display for navi12 
Virtual display is a sw display interface for
bring up and virtualization or for cards without
display hardware.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
44e9e7c96c drm/amdgpu: add ip blocks for navi12 
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
7e17e58bdd drm/amdgpu: set nbio/hdp cg for navi12 
Same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
74b5e509a0 drm/amdgpu: initialize cg/pg flags and external rev id for navi12 
don't enable any cg/pg features yet.

v2: calculate external revision id from revision id so that we can
    differentiate navi12 A0 from A1 directly.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:40 -05:00
Xiaojie Yuan
03d0a073cf drm/amdgpu: initialize reg base for navi12 
Set up the register offset map for navi12.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-08-02 10:30:39 -05:00
Alex Deucher
e9eea90247 drm/amdgpu: drop drmP.h from nv.c 
And fix up the fallout.

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-31 14:33:26 -05:00
Alex Deucher
2ddc6c3ef9 drm/amdgpu: add reset_method asic callback for navi 
Navi uses either mode1 or baco depending on various
conditions.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-30 23:24:17 -05:00
Alex Deucher
d1daf8502e drm/amdgpu: consolidate navi14 IP init 
It's the same as navi10.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Xiaojie Yuan
0377b08823 drm/amdgpu/vcn: enable indirect DPG SRAM mode for navi14 
Enable VCN dynamic powergating for navi14.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:01 -05:00
Xiaojie Yuan
03917df7e5 drm/amdgpu/nv: set vcn pg flag for navi14 
Enable VCN power gating by default.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
d0c39f8cbf drm/amdgpu: enable clock gatings for navi14 
Set appropriate CG flags for navi14.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
James Zhu
e149a2f6ed drm/amdgpu: Enable VCN on navi14 
Add navi14 vcn firmware, and enable VCN on navi14.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Bhawanpreet Lakha
8fceceb69e drm/amd/display: add dm block 
enable DC for navi14.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
ab5e51211c drm/amdgpu: enable sw smu ip for navi14 
same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
4adc0732fc drm/amdgpu: enable psp ip block for navi14 
Same as navi10.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Snow Zhang <Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:18:00 -05:00
Xiaojie Yuan
691f69b6a6 drm/amdgpu: enable virtual display for navi14 
Virtual display is a sw based kms interface for virtualization
and emulation.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Xiaojie Yuan
a29bfd1283 drm/amdgpu: add ip blocks for navi14 
Add the initial IP blocks for navi14

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Xiaojie Yuan
5e71e011ff drm/amdgpu/soc15: add support for navi14 
same as navi10

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:59 -05:00
Xiaojie Yuan
a0f6d926f1 drm/amdgpu/soc15: initialize reg base for navi14 (v2) 
Initialize the IP register base offsets for navi14.

v2: squash in MP, CLK, THM updates

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-18 14:17:58 -05:00
Arnd Bergmann
b5203d16ae drm/amd/amdgpu: hide #warning for missing DC config 
It is annoying to have #warnings that trigger in randconfig
builds like

drivers/gpu/drm/amd/amdgpu/soc15.c:653:3: error: "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
drivers/gpu/drm/amd/amdgpu/nv.c:400:3: error: "Enable CONFIG_DRM_AMD_DC for display support on navi."

Remove these and rely on the users to turn these on.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-16 13:08:59 -05:00
Alex Deucher
f8a7976b75 drm/amdgpu: properly guard DC support in navi code 
Need to add appropriate ifdef.

Acked-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2019-07-08 13:56:42 -05:00