3 Commits

Author	SHA1	Message	Date
Cezary Rojewski	a126750fc8	ASoC: Intel: catpt: PCM operations ... DSP designed for Lynxpoint and Wildcat Point offers no dynamic topology i.e. all pipelines are already defined within firmware and host is relegated to allocing stream for predefined pins. This is represented by 'catpt_topology' member. Implementation covers all available pin types: - system playback and capture - two offload streams - loopback (reference) - bluetooth playback and capture PCM DAI operations differentiate between those pins as some (mainly offload) are to be handled differently - DSP expects wp updates on each notify_position notification. System playback has no volume control capability as it is routed to mixer stream directly. Other primary streams - capture and two offloads - offer individual volume controls. Compared to sound/soc/intel/haswell this configures SSP device format automatically on pcm creation. Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200929141247.8058-7-cezary.rojewski@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>	2020-10-02 15:32:32 +01:00
Cezary Rojewski	a9aa6fb3eb	ASoC: Intel: catpt: Firmware loading and context restore ... For Lynxpoint and Wildcat Point solution, is it host's responsibility to allocate SRAM regions and ensure those already taken are not overwritten with other data until released. Blocks are transferred to SRAM - either IRAM or DRAM - via DW DMA controller. Once basefw is booted, ownership of DMA transfer is lost in favour of DSP. Hosts reponsibilities don't end on initial block allocation and binary transfer. During Dx transitions host must store FW runtime context from DRAM before putting AudioDSP subsystem into lower power state. Said context gets flashed after D0 entry to bring DSP right where it was just before suspending. Load and restore procedures are finalized with SRAM power gating and adequate clock level selection. This power gates unused EBBs and clock speed effectively reducing power consumption. Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200929141247.8058-6-cezary.rojewski@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>	2020-10-02 15:32:31 +01:00
Cezary Rojewski	4fac9b31d0	ASoC: Intel: Add catpt base members ... Declare base structures, registers and extension routines for the catpt solution. Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200929141247.8058-2-cezary.rojewski@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>	2020-10-02 15:32:27 +01:00