19 Commits

Author SHA1 Message Date
Geert Uytterhoeven
be525de9e8 pinctrl: renesas: r8a77990: Optimize fixed-width reserved fields
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 226 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/924ba4505e33180e078ca72a1db8db13c193cbea.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:27 +02:00
Geert Uytterhoeven
f1bef7db75 pinctrl: renesas: r8a77990: Use shorthands for reserved fields
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 40 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c032fce3fff6a6a63dc90f9ab8dfe1f4f3cf6ad6.1649865241.git.geert+renesas@glider.be
2022-05-05 12:02:26 +02:00
Geert Uytterhoeven
d43760b308 pinctrl: renesas: r8a77990: Add RPC pins, groups, and functions
Add pins, groups, and functions for the SPI Multi I/O Bus Controller
(RPC-IF) to the R8A77990 PFC driver.  They are to be used when an
Octal-SPI Flash or HyperFlash is connected.

Redefine the QSPI[01] pin groups using the RPC DQ[0:7] pin data, to save
memory.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ec9735bb3468225e04ac6cb95e11a0e237b2b9ed.1648547080.git.geert+renesas@glider.be
2022-04-20 11:53:46 +02:00
Wolfram Sang
843394c61e pinctrl: renesas: r8a77990: Add drive-strength
According to R-Car Gen3 HW documentation 2.20 onwards, drive-strength is
introduced to r8a77990. It is also documented for r8a774c0. Add it to
the pinctrl driver.

Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220320092542.2308-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-20 11:53:46 +02:00
Geert Uytterhoeven
b67fc1c667 pinctrl: renesas: Remove unused pfc parameter from .pin_to_pocctrl()
The pfc parameter of the .pin_to_pocctrl() method was never used.
It is a relic of the old I/O voltage handling before commit
8775306dcf48092f ("pinctrl: sh-pfc: refactor voltage setting").

Remove the parameter, as it prevents the checker from calling this
function for validating consistency of the pin control tables.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/822133086f32618c7fc920123c6a96f5d4ea7ad6.1640270559.git.geert+renesas@glider.be
2022-02-22 09:57:18 +01:00
Geert Uytterhoeven
5356541360 pinctrl: renesas: r8a77990: Share more VIN pin group data
Pin group vin4_g8 is a subset of vin4_data24_a.
Pin group vin5_high8 is a subset of vin5_data16_a.

This reduces kernel size by 128 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/cfb71c90c19723ba2770f7512f138e4b17857141.1640269757.git.geert+renesas@glider.be
2022-02-22 09:57:18 +01:00
Geert Uytterhoeven
40c845dd87 pinctrl: renesas: r8a77990: Share SDHI pin group data
Pin groups sdhi[01]_data1 are subsets of sdhi[01]_data4.
Pin groups sdhi3_data[14] are subsets of sdhi3_data8.

This reduces kernel size by 56 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2f702b6c6114458a43a77ae04089e7f9e20482e5.1640269757.git.geert+renesas@glider.be
2022-02-22 09:57:18 +01:00
Geert Uytterhoeven
7caf7b3a8f pinctrl: renesas: r8a77990: Share QSPI pin group data
Pin groups qspi[01]_data2 are subsets of qspi[01]_data4.

This reduces kernel size by 32 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/54779df96c1e0fc9ce02786cfd9f66d4cfc063f0.1640269757.git.geert+renesas@glider.be
2022-02-22 09:57:16 +01:00
Geert Uytterhoeven
496da10037 pinctrl: renesas: Add generic support for resizable buses
The VIN_DATA_PIN_GROUP() macro and vin_data{12,16,} unions are used to
define multiple VIN data groups with different numbers of lanes, while
referring to a single array of data pins, thus saving memory.

However, the same feature would be useful for other resizable buses,
like MMC, SDHI, QSPI, LCD, BSC, ...

Rework the mechanism for generic use:
  - Use the new SH_PFC_PIN_GROUP_SUBSET() helper to remove the need for
    bus-specific unions,
  - Rename VIN_DATA_PIN_GROUP() to BUS_DATA_PIN_GROUP(),
  - Rename the macro parameters to better reflect their purposes,
  - Move the macro up, where it belongs.

Update all individual pin control drivers for the above changes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/cccfcfd01eb8ab7a587b084c4ddbf97293bd7291.1640269757.git.geert+renesas@glider.be
2022-02-22 09:55:56 +01:00
Geert Uytterhoeven
c614d12c4b pinctrl: renesas: Rename sh_pfc_soc_operations instances
Some instances of struct sh_pfc_soc_operations are called
"<soc>_pfc_ops", others are called "<soc>_pinmux_ops" or just
"pinmux_ops".  Settle on the first variant, to avoid confusion with
"struct pinmux_ops" in the pinctrl core, and to increase consistency.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2ab33ad1d6a20a57d16922678b78810fa55b7fc0.1640269757.git.geert+renesas@glider.be
2022-02-22 09:55:56 +01:00
Nikita Yushchenko
96310a120c pinctrl: renesas: r8a7799[05]: Add MediaLB pins
This adds pins, groups, and functions for MediaLB devices on Renesas
R-Car E3 and D3 SoCs.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Link: https://lore.kernel.org/r/20211225191713.2187975-1-nikita.yoush@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-01-24 09:59:43 +01:00
Geert Uytterhoeven
d82b924103 pinctrl: renesas: r8a77990: Drop bogus PUEN_ prefixes in comments
The "PUEN_" prefixes are part of the bit names of the PUEN registers,
while the comments should refer to the actual pin names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/9ea85ae8973f6d9b3d10f02f0d9b4ab6a086ec63.1619785375.git.geert+renesas@glider.be
2021-05-11 10:04:42 +02:00
Geert Uytterhoeven
702a5fa2fe pinctrl: renesas: r8a77990: JTAG pins do not have pull-down capabilities
Hence remove the SH_PFC_PIN_CFG_PULL_DOWN flags from their pin
descriptions.

Fixes: 83f6941a42a5e773 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/da4b2d69955840a506412f1e8099607a0da97ecc.1619785375.git.geert+renesas@glider.be
2021-05-11 10:04:42 +02:00
Geert Uytterhoeven
4b6e6c1989 pinctrl: renesas: Move R-Car bias helpers to sh_pfc.h
The Renesas Pin Function Controller driver uses two header files:
  - sh_pfc.h, for use by both core code and SoC-specific drivers,
  - core.h, for internal use by the core code only.

Hence move the R-Car bias helper declarations from core.h to sh_pfc.h,
and drop the inclusion of core.h from SoC-specific drivers that no
longer need it.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20210303132619.3938128-3-geert+renesas@glider.be
2021-03-24 10:38:29 +01:00
Niklas Söderlund
2a9e4f74cd pinctrl: renesas: r8a77990: Add vin4_g8 and vin5_high8 pins
This patch adds vin4_g8 and vin5_high8 support to the R8A77990 SoC.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20210309114930.2433711-4-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-03-10 10:50:26 +01:00
Lad Prabhakar
89ad953e1e pinctrl: renesas: r8a77990: Add QSPI[01] pins, groups and functions
Add pins, groups and functions for QSPIO[01].

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201119130926.25692-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-23 09:43:27 +01:00
Geert Uytterhoeven
27e768a4e7 pinctrl: renesas: Factor out common R-Car Gen3 bias handling
All pin control drivers for R-Car Gen3 SoCs contain identical bias
handling.  Reduce code duplication by moving it to the common pinctrl.c
code.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-6-geert+renesas@glider.be
2020-11-13 15:37:41 +01:00
Biju Das
03522a59a9 pinctrl: renesas: r8a77990: Optimize pinctrl image size for R8A774C0
This driver supports both RZ/G2E and R-Car E3 SoCs.
Optimize pinctrl image size for RZ/G2E, when support for R-Car E3
(R8A77990) is not enabled.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20201019124258.4574-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-11-13 15:37:41 +01:00
Geert Uytterhoeven
077365a941 pinctrl: Rename sh-pfc to renesas
The drivers/pinctrl/sh-pfc subdirectory was originally created to group
pin control drivers for various Renesas SuperH and SH-Mobile platforms.
However, the name "sh-pfc" no longer reflects its contents, as the
directory now contains pin control drivers for Renesas SuperH, ARM32,
and ARM64 SoCs.

Hence rename the subdirectory from drivers/pinctrl/sh-pfc to
drivers/pinctrl/renesas, and the related Kconfig symbol from
PINCTRL_SH_PFC to PINCTRL_RENESAS.

Rename the git branch in MAINTAINERS, too, for consistency.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
2020-09-15 10:04:35 +02:00