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Per fsl,imx-gpcv2.yaml, '#power-domain-cells' is not a valid
property for the top-level gpcv2 node. It is only valid
for its children nodes.
Remove it to fix the following schema warning:
gpc@303a0000: '#power-domain-cells' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/power/fsl,imx-gpcv2.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Per fsl-imx-wdt, 'clock-names' is not a valid property.
Remove it to fix the following schema warning:
watchdog@53fdc000: Unevaluated properties are not allowed ('clock-names' was unexpected)
from schema $id: http://devicetree.org/schemas/watchdog/fsl-imx-wdt.yaml
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Per sram.yaml, address-cells, size-cells and ranges are mandatory.
Pass them to fix the following schema warnings:
sram@78000000: '#address-cells' is a required property
from schema $id: http://devicetree.org/schemas/sram/sram.yaml#
sram@78000000: '#size-cells' is a required property
from schema $id: http://devicetree.org/schemas/sram/sram.yaml#
sram@78000000: 'ranges' is a required property
from schema $id: http://devicetree.org/schemas/sram/sram.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Per imxdi-rtc.yaml, there is only one valid compatible entry and
clock-names is not a valid property.
Change it to fix the following schema warnings:
dryice@53ffc000: compatible: ['fsl,imx25-dryice', 'fsl,imx25-rtc'] is too long
from schema $id: http://devicetree.org/schemas/rtc/imxdi-rtc.yaml#
dryice@53ffc000: 'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/rtc/imxdi-rtc.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There is no need to split dmas in two lines.
Make it more readable by writing it in a single line.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The "reset" key on a few IXP4xx routers were sending KEY_ESC
but what we want to send is KEY_RESTART which will make
OpenWrt and similar userspace do a controlled reboot.
Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-2-98d36264ed6d@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This is a USRobotics NAS/Firewall/router that has been supported
by OpenWrt in the past. It had dedicated users so let's get it
properly supported.
Some debugging and fixing was provided by Howard Harte.
Link: https://lore.kernel.org/r/20231007-ixp4xx-usr8200-v1-1-aded3d6ff6f1@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Node names should be generic, so use 'eeprom' to fix the
following schema warnings:
at24@52: $nodename:0: 'at24@52' does not match '^eeprom@[0-9a-f]{1,2}$'
from schema $id: http://devicetree.org/schemas/eeprom/at24.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Per fsl-imx-sahara.yaml, there should not be a 'fsl,imx51-sahara'
compatible.
Remove it to fix the following schema warning:
imx51-apf51.dtb: crypto@83ff8000: compatible: ['fsl,imx53-sahara', 'fsl,imx51-sahara'] is too long
from schema $id: http://devicetree.org/schemas/crypto/fsl-imx-sahara.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Use the new analog mode SDIO pin definitions on the STM32F7 boards.
Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add SDIO sleep pin definitions that place the pins in analog mode to
save power.
Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The RNG on STM32MP13 offers upgrades like customization of its
configuration and the conditional reset.
The hardware RNG should be managed in the secure world for but it
is supported on Linux. Therefore, is it not default enabled.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Looks like one pinctrl single binding warning sneaked in while we were
implementing the yaml binding. Let's fix the 'pinmux-wl12xx-gpio' does not
match any of the regexes warning by adding -pins suffix.
Signed-off-by: Tony Lindgren <tony@atomide.com>
The sleep pins never got added earlier probably because the driver was not
behaving correctly with the sleep pins. We need the sleep pins to prevent
the modem from waking up on it's own if the reset pin glitches in deeper
SoC idle states.
Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Pavel Machek <pavel@ucw.cz>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Message-ID: <20230911035828.36984-1-tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The AM3517 has one ethernet controller called davinci_emac.
Configuring the alias allows the MAC address to be passed
from the bootloader to Linux.
Signed-off-by: Adam Ford <aford173@gmail.com>
Message-ID: <20230906095143.99806-2-aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Ethernet PHY interrupt pin is routed to GPIO_58. Create a
PHY node to configure this GPIO for the interrupt to avoid polling.
Signed-off-by: Adam Ford <aford173@gmail.com>
Message-ID: <20231005000402.50879-2-aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The pinmux for LED3 and LED4 are incorrectly attached to the
omap3_pmx_core when they should be connected to the omap3_pmx_wkup
pin mux. This was likely masked by the fact that the bootloader
used to do all the pinmuxing.
Fixes: 0dbf99542caf ("ARM: dts: am3517-evm: Add User LEDs and Pushbutton")
Signed-off-by: Adam Ford <aford173@gmail.com>
Message-ID: <20231005000402.50879-1-aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Drop omap36xx compatible as done in other omap3630 devices.
This has apparently fallen through the lattice.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Message-ID: <20231004065323.2408615-1-andreas@kemnade.info>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add also the level-shifter flag to avoid probe failure in magnetometer
probe.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Message-ID: <20230927173245.2151083-4-andreas@kemnade.info>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This will allow frequency-scaling for the cpu-cores.
Operating frequencies and voltages have been taken from Rockchip's
downstream kernel.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829214004.314932-10-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
For bring-up of the non-boot cpu cores the enable-method for RK3036 can be
re-used.
This adds a (small) chunk of SRAM for execution of the SMP trampoline code
and the respective enable-method property to the cpus.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829214004.314932-8-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
In order to support bring-up of the non-boot cores, this patch adds the
reset controls for the cpu cores.
They are required/will be used by the Rockchip platsmp driver.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829214004.314932-6-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Currently the Rockchip timer source clocks are set to xin24 for no obvious
reason and the actual timer clocks (SCLK_TIMER*) will get disabled during
boot process as they have no user. That will make the SoC stuck as no timer
source exists.
Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi")
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829203721.281455-12-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Like most other Rockchip ARM SoCs, the PL330 needs the
arm,pl330-periph-burst quirk in order to work as expected.
Add it.
Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi")
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829203721.281455-10-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The register address for i2c0 is missing a 0x to mark it as hex.
Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi")
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829203721.281455-6-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
atmel,rtt-rtc-time-reg is a mandatory property and encodes the GPBR
register used to store the time base when the RTT is used as an RTC.
Align the RTT with what's currently done for sam9x60ek and sama7g5ek,
and enable it by default even if RTC is also enabled.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
[nicolas.ferre@microchip.com: adapt to newer kernel]
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20230928143644.208515-1-nicolas.ferre@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
The Anbernic RG-Nano is a small portable game device based on the
Allwinner V3s SoC. It has GPIO buttons on the face and side for
input, a single mono speaker, a 240x240 SPI controlled display, a USB-C
OTG port, an SD card slot for booting, and 64MB of RAM included in the
SoC. There does not appear to be a crystal feeding the internal RTC so
it does not keep proper time (for me it ran 8 hours slow in a 24 hour
period). External RTC works just fine.
Working/Tested:
- SDMMC
- UART (for debugging)
- Buttons
- Charging/battery/PMIC
- Speaker
- RTC (external RTC)
- USB
- Display
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20230929144441.3409-5-macroalpha82@gmail.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Add the EHCI and OHCI controller to the Allwinner v3s to support using
USB in host mode.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230929144441.3409-3-macroalpha82@gmail.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Add pinctrl nodes for pwm0 and pwm1.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230929144441.3409-2-macroalpha82@gmail.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
stm32mp15-pinctrl.dtsi contains nearly all pinctrl groups collected from
all boards. Most of them end up unused by a board and only waste binary
space. Add /omit-if-no-ref/ to the groups to scrub the unused groups
from the dtbs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add the HASH support on stm32mp131.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
GPIO keys and LEDs are not part of the SoC, so move them to top-level to
fix dtbs_check warnings like:
qcom-ipq8064-rb3011.dtb: soc: gpio-keys: {'compatible': ['gpio-keys'], ... should not be valid under {'type': 'object'}
from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230924183914.51414-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Fixed regulator put under "regulators" node will not be populated,
unless simple-bus or something similar is used. Drop the "regulators"
wrapper node to fix this.
Fixes: 2c5e596524e7 ("ARM: dts: Add MDM9615 dtsi")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230924183914.51414-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
regulator-fixed does not have a "regulator-type" property:
qcom-apq8060-dragonboard.dtb: regulator-fixed: Unevaluated properties are not allowed ('regulator-type' was unexpected)
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230924183914.51414-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
regulator-fixed does not have a "regulator-type" property:
qcom-apq8064-ifc6410.dtb: regulator-ext-3p3v: Unevaluated properties are not allowed ('regulator-type' was unexpected)
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230924183914.51414-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Bindings expect clocks to be in different order:
qcom-sdx65-mtp.dtb: mmc@8804000: clock-names:0: 'iface' was expected
qcom-sdx65-mtp.dtb: mmc@8804000: clock-names:1: 'core' was expected
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230924183335.49961-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
DSI node does not accept nor use "label" property:
qcom-apq8064-asus-nexus7-flo.dtb: dsi@4700000: Unevaluated properties are not allowed ('label' was unexpected)
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230924183335.49961-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
